Error in uvm_config_db

UVM
,
8

Yes, thank you for your all answers.

So when i try this code :

module top_tb;
  import uvm_pkg::*;
`include "uvm_macros.svh"
 
  virtual apb_interface slave_interface;
  virtual ahb_interface master_interface;
 
  initial begin 
    $timeformat ( -6, 3, " us", 10);
 
    uvm_config_db#(type(slave_interface))::get(null, "", "slave_interface", slave_interface);
    uvm_config_db#(type(master_interface))::get(null, "", "master_interface", master_interface);
 
    uvm_config_db#(type(slave_interface))::set(null, "uvm_test_top.env.slave_agent*", "vif", slave_interface);
    uvm_config_db#(type(master_interface))::set(null, "uvm_test_top.env.master_agent*", "vif", master_interface);
 
    run_test("no_test") ;
  end

I have a error when i want to simulate like it doesn’t find the port to connect interface ahb and apb