UVMC, connection of systemVerilog to SystemC using non blocking transport

UVM
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Hi, dear forum members

Could you send me a complete example of connecting systemVerilog to SystemC with UVMC using non-blocking transport? or give good advice on where I can find examples? During My research, I have found only examples of blocking transport.

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In reply to david200002:

Hi, dear forum members
Could you send me a complete example of connecting systemVerilog to SystemC with UVMC using non-blocking transport? or give good advice on where I can find examples? During My research, I have found only examples of blocking transport.

David,

At present the only examples you see in the package are ones that send config extensions
via nb_transport_fw() that uses early completion semantics. These are under examples/config_exts/

There is a new UVMC release 2.3.3 coming out soon that will fully demonstrate 4-phase
operations using nb_transport_fw(), nb_transport_bw() function calls.

– johnS