Within our testbench, UVMC was utilized to facilitate communication between UVM and SystemC. Rather than being instantiated within sc_main, the SystemC modules are generated within a DPI-C function invoked from the SystemVerilog side in an initial block.
However, an error is reported when running the simulation: Error: (E521) immediate notification is not allowed during update phase or elaboration
This error is from SV2C_sv_ready() function in uvmc_commands.sv, bit sv_is_ready = SV2C_sv_ready();
In the definition of SV2C_sv_ready(), calling sv_ready_e.notify() triggers the error. Based on the code, it appears that the SV2C_sv_ready() function expects that SystemC modules have been instantiated and sc_start() executed before its invocation. However, because SV2C_sv_ready() is invoked during systemverilog global variable initialization and SystemC modules are created by a DPI-C which is called in the initial block, it becomes challenging to satisfy this sequence requirement.
Hence my questions are as follows:
Why is SV2C_sv_ready triggered during the SystemVerilog global variable creation stage, and can this function be user-initiated instead?
Is there any guideline for employing UVMC when SystemC modules are initialized within a user-defined function rather than sc_main()?
To answer your first question, this is a little trickiness that is trying to
resolve ordering of SV elaboration with regard to SC-side UVMC operations.
There isn’t really any standard that dictates semantics for this and so I think
this code was trying to be as accommodating to the different simulator vendors
as possible. The whole idea is that we want to hold back a number of SC-side
UVMC operations until we have some level of confidence that SV elaboration has
occurred and SV as entered at least the first init phase. The functions that
call wait_sv_ready() basically want a confirmation of this so that they know
that a proper DPI package scope for the SV UVMC package can be established in
order to call DPI functions on the SV side.
You cannot assume SV hierarchical scopes of any kind are valid until SV has
fully gone through its elaboration phase.
Could it be user initiated instead ? Hmmm. I suppose you can try but you would
still have to make sure that SV UVMC package scope is valid in some way before
calling it.
For your 2nd question I’m not sure what you mean by “employing UVMC”.
Basically SystemC elaboration occurs when the top-level module constructor
is called which then calls its children constructors which call their children,
etc.
But it is only when sc_start() is called that all the SC processes are first
spun up. It is at that point that UVMC runtime operations can begin.
But UVMC connections (i.e. calls to uvmc_connect() will need to be done during
the SC construction (aka elaboration phase) prior to commencement of sc_start().