This topic area focuses on formal-based techniques, ranging from formal property checking to clock-domain crossing (CDC) verification. Assertion-based verification (as it relates to formal property checking) is also covered in this topic area.
Formal-Based Techniques Courses
Formal-Based Techniques Resources
Synthesizing Assertions into Hardware for Faster Silicon Debug
Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
A Unified Verification Flow Using Assertion Synthesis Technology
As SOC integration complexity grows tremendously in the last decade, traditional blackbox checker based verification methodology fails to keep up to provide enough observability needed. Assertion-based verification (ABV) methodology is widely recognized as a solution to this problem.
Mentor Graphics Questa CDC Adopted by iD Corporation for Clock Domain Crossing Verification Signoff
The vast majority of today’s SoC and FPGA designs contain multiple asynchronous clocks and companies such as iD need a comprehensive solution for CDC verification. Using Questa CDC’s static analysis capabilities, iD’s design teams can quickly and easily uncover bugs in asynchronous circuits and avoid discovering them late in the design cycle or during lab verification.
Verification Solutions that Help Reduce Bug Cost
Bugs found before simulation obviously have the lowest cost. Bugs found at block or subsystem simulation are generally easier to debug and incur a lower cost to fix versus bugs found at high levels of integration—such as chip- and system-level simulation.
Applied Micro Circuits Corporation (AMCC) adopts Questa CDC for their complex clock domain crossing verification.
A recent high-performance network processor presented a new challenge for the AMCC team. The processor consisted of a PowerPC embedded processor core and a multi-clock domain SoC that includes Ethernet and other standard interfaces.
Using Formal Verification to Check SoC Connectivity Correctness
Formal verification offers a solution that is quick, exhaustive and allows for efficient debug. It’s true that traditionally, chip-level formal verification is impractical.
Planning Formal Verification Closure
This paper introduces a process (consisting of a set of recommendations) for achieving static formal verification closure.
Five Steps to Quality CDC Verification
With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important.
A Comparison of Metastability Modeling Methods
With asynchronous clocks common place in today's ICs, designers need a solution to verify that the design's functionality is not impacted by the non-deterministic effects of metastability.
The Need for an Automated Clock Domain Crossing Verification Solution
Clock domain crossings (CDC) continue to be a trouble spot for functional verification. With the number of clock domains increasing in today's complex system designs, the ability to thoroughly verify CDC has become even more important.
Improving Quality and Time-to-Market with Formal Verification
This archived web seminar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification.
Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models
This archived web seminar focuses on how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior.
Industrial-Strength Clock Domain Crossing Verification
This archived web seminar will explain each of these steps in CDC verification and demonstrate how Questa CDC Verification automates these steps.
Clock-Domain Crossing Verification for FPGAs
This archived web seminar talks about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your FPGA is free of CDC issues.