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  • Home /
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  • Formal-Based Techniques

Formal-Based Techniques

Formal-Based Techniques

This topic area focuses on formal-based techniques, ranging from formal property checking to formal coverage closure to sequential logic equivalence checking.

Featured Session - Should I Kill My Formal Run? Part 1:

What You Can Do While the Formal Run is In-Progress

Overview:

Imagine you have a formal job currently running in another window, and you are in a quandary about whether to keep it going or to kill it to save computer resources and time. In this segment we will show you the information you can use to decide whether to continue or stop. 

View archived recording.

Featured Session - Should I Kill My Formal Run? Part 2:

What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success

Overview:

In this segment we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.

View archived recording.

Formal-Based Techniques Courses

Handling Inconclusive Assertions in Formal Verification

Subject Matter Expert - Jin Hou | Handling Inconclusive Assertions in Formal Verification Course

In this course, you will be introduced to techniques to help formal tools solve inconclusive assertions. You will also learn tool options to help convergence, introduce techniques for reducing assertion and design complexity.

Formal Coverage

Formal Coverage Course | Subject Matter Expert - Mark Eslinger | Formal-Based Techniques Topic

Formal coverage is a hot topic these days. Simulation has a number of metrics for helping determine when verification is done. These include code coverage, assertions coverage, transaction coverage, and functional coverage to name a few.

Sequential Logic Equivalence Checking

Sequential Logic Equivalence Checking Course | Subject Matter Expert - Jin Hou | Formal-Based Techniques Topic

In this course, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

Power Aware CDC Verification

Power Aware CDC Verification Course | Subject Matter Expert - Kurt Takara | Formal-Based Techniques Topic

In this course, you will learn the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.

Formal Assertion-Based Verification

Formal Assertion-Based Verification Course | Subject Matter Expert - Mark Eslinger | Formal Based Techniques Topic

In this course the instructors will show how to get started with direct property checking.

Formal-Based Technology: Automatic Formal Solutions

Formal-Based Technology: Automatic Formal Solutions Course | Subject Matter Expert - Mark Eslinger | Formal Based Techniques Topic

After a brief introductory session outlining the general architecture of formal apps, in each subsequent session of the course will deep dive on a specific verification challenge and the corresponding formal application.

Clock-Domain Crossing Verification

Clock-Domain Crossing Verification (CDC) Course | Subject Matter Expert - Harry Foster | Formal-Based Techniques Topic

This course introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.

Questa® Formal Verification Resources

  • Featured
  • Articles
  • White Papers
  • Demos
  • On-Demand
  • Seminars
  • Blog Posts
  • Product Information

What Is Formal, And How It Works Under-the-Hood

  • What is Formal, Anyway?
  • Instant Formal Expert

Success Stories

  • How Microsemi Uses Questa Formal Connectivity Check to Improve Quality and Productivity
  • Cypress Adopts Questa Formal Apps to Create Pristine IP

Formal Verification Seminar - Download the Session Slides!

  • Formal Verification Tips for Success
  • Formal Verification: Automation and Tips for Success

Press Release

  • Mentor Graphics Expands Formal Verification's Reach with New Cross-Platform GUI and Apps for Sequential Logic Equivalence Checking and CDC Gate-Level Analysis

Stuck on a Desert Island without Simulation – Only Formal!

  • How Do I Verify My Rescue Drone's RTL
  • An Exhaustive 1-2 Punch for RTL Signoff
  • Select and Run Automated Formal Apps
  • Setup a Formal Testbench
  • Use Formal to Check Logic Faults
  • Close the Verification Loop

Microsoft Xbox® Formal Success

  • How the X-Box Program Has Adopted Formal

ARM® Techcon Paper Report

  • Advanced Verification Management and Coverage Closure Techniques
  • How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps
  • ARM® Techcon 2014 Proceedings

Featured Formal-Based Techniques Verification Horizons Articles

  • Formal Bug Hunting with “River Fishing” Techniques
  • Ten Rules to Successfully Deploy Formal
  • Formal Apps Take the Bias Out of Functional Verification
  • It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
  • RTL Glitch Verification
  • Debugging Inconclusive Assertions and a Case Study
  • Formal Verification: Not Just for Control Paths
  • How Formal Techniques Can Keep Hackers from Driving You into a Ditch
  • Minimizing Constraints to Debug Vacuous Proofs
  • Evolving the Use of Formal Model Checking in SoC Design Verification
  • Functional Coverage Development Tips: Do's and Don'ts
  • Formal and Assertion-Based Verification of MBIST MCPs
  • Starting Formal Right from Formal Test Planning
  • Life Isn't Fair, So Use Formal
  • Confidence in the Face of the Unknown: X-state Verification
  • Using Formal Analysis to "Block and Tackle"
  • The Formal Verification of Design Constraints
  • The Top Five Formal Verification Applications

Featured Formal-Based Techniques White Papers

  • Formal Apps Take the Bias Out of Functional Verification
  • Reset Verification in SoC Designs
  • Formal Techniques for Optimizing ISO 26262 Fault Analysis
  • Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking
  • Questa® CoverCheck: An Automated Code Coverage Closure Solution
  • Register Verification: Do We Have Reliable Specification?
  • Is Your Power Aware Design Really X-Aware?

Questa® PropCheck

  • Overview
  • Cone of Influence
  • Debug a Firing
  • Properties Tab
  • Property Editor
  • Run Monitor/Details
  • Schematic
  • Source Window
  • Waveform View
  • Run Formal

Questa® AutoCheck

  • Design Checks, Source & FSM Debug

Questa® Connectivity Check

  • Assertions & Waveforms

Questa® CoverCheck

  • Details, Coverage Checks & Source Debug

Questa® Register Check

  • Memory Mapped Register Checkers

Questa® SecureCheck

  • Properties Tab, Waveform & Schematic Views

Questa® X-Check

  • Find X Corruption Views

Featured Formal-Based Techniques On-Demand Technical Sessions

  • Should I Kill My Formal Run? Part 1: What You Can Do While the Formal Run is In-Progress
  • Should I Kill My Formal Run? Part 2: What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success
  • How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques
  • How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration
  • New School Connectivity Checking
  • New School Coverage Closure
  • Improving Quality and Time-to-Market with Formal Verification

Featured Formal-Based Techniques Seminars

  • What Is Formal, And How It Works Under-the-Hood
  • Formal Verification Tips for Success
  • Stuck on a Desert Island without Simulation – Only Formal!
  • New School Formal Verification

Featured Formal-Based Techniques Blog Posts

  • The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification - Joe Hupcey |||
  • The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC
  • Leveraging Data Independence and Non-Determinism - Part 6
  • Memory Abstraction - Part 5
  • Counter Abstraction - Part 4
  • Assertion Decomposition - Part 3
  • Reducing the Complexity of Your Assumptions - Part 2
  • Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take - Part 1
  • Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers
  • OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench
  • No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
  • Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them
  • How to Become a Formal Expert and Impress your Friends and Boss!
  • How to Save a Ton of Time and Energy by Prioritizing Faults with Exhaustive Formal Analysis Before Launching Detailed Fault Verification
  • DVCon China: Formal Technology Is Set for Growth in Asia
  • How To Connect Your Testbench to Your Low Power UPF Models
  • How Formal Techniques Can Keep Hackers from Leaving You in the Cold
  • 3 Things About UPF 3.0 You Need to Know Now
  • How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC
  • 5 Things I Learned at the 2016 SAE World Congress
  • DVCon USA 2016: Heralding Formal's New Wave
  • Goal posts Aren't Only for Football – Use Them in Formal Analysis Too!
  • Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!
  • Formal Tech Tip: How Good Properties Can be Over-constrained and How to Fix It
  • Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification
  • How Formal Techniques Can Keep Hackers from Driving You into a Ditch (Part 2 of 2)
  • How Formal Techniques Can Keep Hackers from Driving You into a Ditch (Part 1 of 2)

Exhaustive, Automated Solutions for Complex Verification Challenges

Questa® formal-based technologies offer a broad spectrum of formal solutions and applications which complement simulation in a number of key areas. Questa Formal Verification Apps boost verification efficiency and design quality by exhaustively addressing verification tasks which are difficult to complete with traditional methods, yet don’t require formal or assertion-based verification experience.

Learn more.

Datasheets
  • Questa® Formal Applications Datasheet
  • Questa® SLEC

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