Formal-Based Techniques

Securing the Electronics Development Chain with IC Integrity Solutions

In this session we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking for this very complex IC integrity challenge.

How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification

In this session, we will start by reviewing the unique capabilities in Siemens EDA's formal solutions, then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim. Plus: if you already have some expertise in property checking, we will also share several apps that leverage this experience to address challenges like validating the completeness of your verification plan, processor/RISC-V verification, and FPGA implementation.

From Model to Implementation with High-Level Synthesis

In an MBSE flow, developers need to make informed choices on the implementation of functions in the system model. This talk will explore how High-Level Synthesis (HLS) can be used to deliver the data needed to make critical design trade-off decisions. We will also cover how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.

Siemens and the US Government - Mitigating Microelectronics Development Challenges

Siemens: Mitigating Microelectronics Development Challenges | Subject Matter Expert - Rich Powlowsky | Aerospace and Defense Verification Tech Day

Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle. Together with Siemens Govt. Technologies and the broader Siemens portfolio, we offer multi-domain, commercial platforms to the Dept. of Defense community: including secure design, digital engineering and trusted supply chain solutions.

Formal 101 - Fast, Scalable Formal Verification Made Easy

In this session, we will give an overview of how to apply basic abstractions, how to set up & optimize constraints, and where and how to leverage Data Independence & Non-Determinism.

Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.

Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.

Formal 101 – Data Independence and Non-Determinism Made Easy

In this session, we will show how with a little design knowledge and forethought on your part, you can leverage these two principles to cut down your formal analysis to a matter of minutes vs. hours.

Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy

In this session, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.

Questa® Register Check Demo

Register Check Demo Session | Subject Matter Expert - Mark Eslinger | Formal-Based Technology: Automatic Formal Solutions Course

This session will demo memory mapped register checkers generated results that can be debugged in the using Questa® Register Check.

IP Security: Keys to Early Identification of Security Vulnerabilities

In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

Questa® X-Check Demo

This session will demo finding X corruption in your design using Questa® X-Check.

Questa® PropCheck Demo

This session will demo the Questa® PropCheck tool and will review features including the details window, properties window, along with source, waveform and schematic debug features.

Questa® CoverCheck Demo

This session will demo the Questa® CoverCheck tool and will review features including the details window, coverage checks window, and source debug features.

Questa® AutoCheck Demo

This session will demo the Questa® AutoCheck tool and will review features including the details window, design checks window, source, waveform, schematic, and fsm debug features.

The Future of Automotive and its Impact on Safety

This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.

Equivalence Checking for FPGA

In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

SLEC for Safety Mechanism

In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.

SLEC for Low Power Clock Gating

In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.

SLEC Introduction

In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.

SLEC for Design Optimization

In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.

SLEC for Bug Fix / ECO

In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.

Advanced Topic

In this session, you will be introduced to the techniques of separating functions, data-independence, non-determinism, and bug hunting that are very useful for formal verification.

Design Complexity Reduction

In this session, you will be introduced to techniques to reduce the complexity of designs for formal verification, including understanding what formal is analyzing, easy ways to reduce design complexity, counter remodeling and memory remodeling examples.

Assertion Complexity Reduction

In this session you will be introduced to the techniques that reduce the complexity of assumptions and checkers for formal verification, including under-constraining, over-constraining, assertion decomposition, adding “helper” assertion, assume-guarantee, and Questa® QFL assertion libraries.

Easy Solutions

In this session you will be introduced to easy solutions for handling inconclusive assertions by exploring tool options, and how to know where formal is stuck at.

Trouble: Three CDC Glitches That Only a Netlist Will See

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs

Formal 101 – Setting Up & Optimizing Constraints

Formal 101 – Basic Abstraction Techniques | Subject Matter Expert - Mark Eslinger | Siemens EDA 2021 Functional Verification Webinar Series

In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.

Low Power Considerations for Verification

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.

Formal 101 – Basic Abstraction Techniques

In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.

“Bounded Proof” Sign-Off with Formal Coverage

In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.

Applying Big Data to Next-Generation Coverage Analysis and Closure

This session will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration.

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

This session will present a "spiral refinement" bug hunt methodology that captures the success factors and guides the deployment of various formal techniques.

Automatic Formal Verification - Questa Static and Formal Apps

In this session, you will gain an understanding of the automatic formal applications that can be used to solve current design and verification challenges.

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

The ABC of Formal Verification

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.

I'm Excited About Formal...My Journey From Skeptic To Believer

This web seminar documents an unlikely journey into formal for a verification engineer who’s spent an entire career using simulation.

Reducing Area & Power Consumption with Formal-based ‘X’ Verification

Reducing Area and Power Consumption while Increasing Performance with Formal-based ‘X’ Verification Session | Ping Yeung - Subject Matter Expert

In this session we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process.

Should I Kill My Formal Run? Part 1: Formal Run is In-Progress

In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.

Get Your Bits Together: SystemVerilog Structures and Packages

In this session, you will learn best practices for structures and packages in the SystemVerilog language and how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused.

Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal

In this session, you will learn how formal analysis works, and you can create an effective "formal testbench" with very basic, easy-to-write properties.

Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, validating low power clock gating and more.

Deadlock Verification For Dummies - The Easy Way Using SVA and Formal

In this session we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!

Mind the Gap(s): Closing and Creating Gaps Between Design and Verification

This workshop will examine several gaps in development processes that can result in verification escapes, and suggest solutions that can prevent bugs from finding their way into customer deployments.

Questa® PropCheck GUI Demo - Run Formal

In this session, you will learn how to run Formal from the PropCheck GUI

Questa® PropCheck GUI Demo - Waveform View

In this session, you will learn more about the Waveform View.

Questa® PropCheck GUI Demo - Source Window

In this session, you will learn how to use the Source Window.

Questa® PropCheck GUI Demo - Schematic

In this session, you will learn how to use the Schematic view.

Questa® PropCheck GUI Demo - Run Monitor/Details

In this session, you will learn how to rerun Formal in the GUI.

Questa® PropCheck GUI Demo - Property Editor

In this session, you will learn features of the Property Editor.

Questa® PropCheck GUI Demo - Properties Tab

In this session, you will learn some of the features of the Properties Tab.

Questa® PropCheck GUI Demo - Debug a Firing

In this session, you will learn how to debug a firing in the GUI.

Questa® PropCheck GUI Demo - Cone of Influence

In this session, you will learn more about the Cone of Influence window features.

Questa® PropCheck GUI Demo - Overview

In this session, you will be shown a top level overview of the Questa® PropCheck GUI.

Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success

Should I Kill My Formal Run - Part 2: What You Can Do Beforehand to Avoid Trouble and Set Yourself Up for Success Session | Subject Matter Expert - Mark Eslinger | Academy Live Web Seminar

In this session we assume you are about to kick off a formal analysis, and want to make sure you will avoid the most obvious pitfalls in setting up your formal testbench, the DUT, and the runner scripting.

Formal Bug Hunting with “River Fishing” Techniques

In this session you will learn how our methodology leverages your functional simulation activities and starts formal verification from interesting “fishing spots” in the simulation traces.

Why Reset Domain Crossing Verification is an Emerging Requirement

In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.

Debugging Your Design in a Heterogeneous Environment

In this session we will discuss Mentor's solution to address debug needs of today's complex environment using Questa® Visualizer Debug.

First Pass Success Depends on Holistic Planning that Includes Formal

In this session you will learn how to integrate multiple formal solutions into a holistic planning process and a metric-driven verification work-flow.

Clock-Domain Crossing Analyses and Verification

This session explains the importance of a complete CDC methodology to produce error-free silicon.

Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.

Questa® PropCheck GUI Demo - Coverage

In this session, you will learn how Formal Coverage is viewed in the GUI.

Industry Advancements Required to Close the Power Management Verification Gap

In this session, you will learn how Qualcomm overcomes their Power Verification Challenges and how they utilize Power Aware Verification techniques.

How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques

In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

In this session we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

It’s Been 24 Hours - Should I Kill My Formal Run?

In this session we will show how to make an informed decision using “engine health” monitoring, a snapshot of the active logic being used by the analysis, and making an honest appraisal of the assumptions you applied at the beginning of the run.

Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC Level

CDC Analysis at SOC level involves huge challenges in terms of capacity, quality of results, and ease of debug, dependencies and ownership of IPs. The flagship SOC designs are typically the biggest and the most complex.

What is Formal, Anyway?

In this session, you will learn what formal property checking is about: how formal differs from simulation, how constraints on expected inputs apply in the formal world, how it provides exhaustive results, and more.

Instant Formal Expert

What are formal property checking engines and how do they work? Why are they incredibly powerful for some properties, but not so good for others? What's the state of the art and what's coming in the near future? In this session, we'll review the fundamentals as well as the recent breakthroughs that are driving advances in performance and capacity. Join us to instantly become a formal expert!

How Formal Reduces Fault Analysis for ISO 26262 - Part 3

DVCon 2018 | How Formal Reduces Fault Analysis for ISO 26262

In this session, you will learn how Formal reduces fault analysis for ISO 26262.

Inconclusive Debug Demo

This session will demo how to debug an inconclusive property using Questa PropCheck.

Editor Insight

This editor insight session provides an introduction and motivation for our new course, which is focused on handling inconclusive assertions in formal property checking.

Formal Coverage Demo

This session will demo formal coverage using Questa PropCheck.

Property Debug Demo

This session will demo property debug using Questa PropCheck.

Coverage & Plan-Driven Verification for FPGAs

This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.

Formal Coverage Introduction & Overview

Course Introduction & Overview Session | Subject Matter Expert - Mark Eslinger | Formal Coverage Course

In this session, you will be introduced to the Formal Coverage course.

Formal for Over-Constraint and Reachability Analysis

In this session we’ll review what makes a design observable and controllable. Next we’ll look at doing reachability analysis for understanding if a design is a good candidate for applying formal techniques.

Formal Coverage for Inconclusive Debug

In this session we’ll review what inconclusive properties are and why they happen. We’ll then look at some easy tool based methods to help resolve inconclusives.

Formal Coverage for Property Debug

This session will review the definition of a vacuous or uncoverable property and the main reasons why these property bugs exist

Formal Coverage vs. Simulation Coverage

This session will explore the various aspects of formal coverage. We’ll start by reviewing the major components of simulation coverage metrics including code coverage, assertions coverage and functional coverage.

Why Gate Level CDC is Needed (Even After RTL CDC Closure!)

In this session, you will learn how to leverage inputs from RTL CDC verification to automate and accelerate gate-level CDC verification closure with very "low noise" results.

How Formal Reduces Fault Analysis for ISO 26262

In this session, you will learn how Formal tools provide unique capabilities that are essential for any automotive functional safety flow.

My Experience with Questa® CDC Bring-Up

In this session, you will learn from Knowles Intelligent Audio on how they utilize Questa® CDC to achieve successful results.

Close the Verification Loop

In this session, you learn how to close the verification loop by electronically mapping all your progress back to your original plan.

Use Formal to Check Logic Faults

In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.

Setup a Formal Testbench

In this session, you will learn how to setup a formal testbench and related verification methodology efficient property checking and analysis.

Select and Run Automated Formal Apps

In this session, you learn how to select & run automated formal apps to expedite your verification effort without writing any SVA code.

An Exhaustive 1-2 Punch for RTL Signoff

In this session, you will learn from Microsemi® on how they utilize Questa® AutoCheck and CoverCheck to reach RTL signoff.

How Do I Verify My Rescue Drone's RTL

In this session you will learn how to translate verification requirements into a machine-readable verification plan and related coverage goals.

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

What Is CDC Protocol Verification, and Why You Absolutely Need It To Prevent Bugs in Your Silicon Session | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.

Industry Trends in Today’s Functional Verification Landscape

In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.

Enterprise Debug for Formal

In this session you learn more about formal-centric enterprise debug.

Register Check - Memory Mapped Register Verification

Memory Mapped Register Verification Session | Subject Matter Expert - Mark Eslinger | Formal-Based Technology: Automatic Formal Solutions Course

In this session we’ll take a quick overview of memory mapped verification and some of the challenges users face with verifying these design constructs.

Questa® Connectivity Check Demo

Connectivity Check Demo Session | Subject Matter Expert - Mark Eslinger | Formal-Based Technology: Automatic Formal Solutions Course

This session will demo assertions and results and a quick debug showing the QFL waveforms using Questa® Connectivity Check.

Connectivity Check - Connectivity Verification Overview & Challenges

This session we’ll take a quick look at the various challenges in doing connectivity verification with current methods. We’ll also look at a number of connectivity checking applications.

Using a Chessboard Challenge to Discover Real-world Formal Techniques

In this session, Oski describes formal techniques included case-splitting, symmetry reduction, assume-guarantee and disabling lower proof depths used to solved a chessboard problem.

Orange is the New Black, Reset Verification is the New CDC

In this session we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.

Formal Verification Tips & Tricks for Fun & Profit

In this session you will learn SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, simple tips to setup the analysis for rapidly reaching a solution, and benefiting from "coverage" in a formal context.

Verification Patterns: An Optimized Reusable Solution

In this session, we introduce the new Verification Academy Patterns Library and present pattern examples that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.

X-Check - Mitigating X Effects in Your Verification

In this session we’ll take a quick look at the various types of X effects and how they can impact your design. We’ll also look at some common sources of X which are the originators of these effects.

Questa® SecureCheck Demo

This session will demo the Questa® SecureCheck tool and will review features including the details window, properties tab, waveform and schematic views.

Questa® CDC Power Aware Demo

This session demonstrates the Questa® CDC Power Aware solution for verifying low power designs including clock domain crossing (CDC) and voltage domain crossing (VDC) paths.

SecureCheck - How Secure is your Design?

This session will show how to exhaustively prove the integrity of the hardware root of trust with your RTL and a clear text, human and machine readable spreadsheet to specify the critical storage and allowed access paths.

Trends in Formal Verification: Not Just for Experts Anymore!

In this session, industry trends will be presented with an emphasis on formal verification technology adoption and solutions.

Formal Model Checking: From Oblivion to a Pillar of Success

This session will describe how formal methods went from being used opportunistically to a central place in the verification methodology of the RAPID SoC to help the Oracle team achieve its verification goals of finishing on schedule and achieving first pass silicon success.

How Secure is Your System?

This session will discuss how the Secure Check app can be the foundation of your "root of trust".

New Coverage Closure Techniques

In this session you will learn how a mix of formal apps and methodologies including, recording and tracking coverage with the Unified Coverage Database (UCDB), as per the Accellera Unified Coverage Interoperability Standard (UCIS).

How to Keep UPF from Ruining Your CDC Analysis

In this session we will discuss the effects of advanced low power design on CDC by the addition of isolation cells, retention cells, level shifters, and dynamic voltage scaling.

New School Connectivity Checking

This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.

Describing Low Power Logic with UPF

This session describes the clock-domain crossing requirements for low power designs and explains the CDC issues introduced by power control logic.

Integrating Power Aware CDC into a Design Flow

This session describes a low power verification methodology and how the Questa® Power Aware CDC solution may be integrated into your design flow.

Understanding Low Power Impact on CDC Logic

This session describes the impact of low power design techniques on design and CDC logic and also explains dynamic voltage and frequency scaling (DVFS) and its effect on CDC design and verification.

Power Aware CDC Introduction and Overview

Introduction and Overview Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session introduces the design challenges created by low power designs and the implications that these designs have on CDC verification.

Introduction to Formal Assertion-Based Verification

In this session we will learn about various formal verification techniques; what they are, how to utilize them, and benefits received from advanced formal technologies.

Basic Formal Closure, (Black Boxing and Cutpoint)

At some point formal engines will begin to struggle under the weight of the state space. This session will show two simple techniques to safely limit the states the engines need to process, enabling more in-depth results.

PropCheck - Formal Model Checking

In this session we'll share some basic tips for getting started with direct property checking, how to setup the analysis for rapidly reaching a solution, and how to answer the question, “Do I have enough assertions?"

Introduction to Automated Formal Apps

This session will introduce you to Formal Apps; what they are, how they are structured and what is available today.

CoverCheck - Accelerating Coverage Closure

This session will show how automated formal techniques can be used to keep the project moving forward by exhaustively determining the reachability or unreachability of coverage elements, grant persistent waivers to areas that can be safely excluded, and how the master coverage database can be automatically updated with the current coverage score.