Issue with Defining a 2D Non-Deterministic Array in Formal Verification Property

SystemVerilog
1

I am working on formal property verification, and I need to define a 2D non-deterministic array within a property. Below is the property I have defined:

property order_check;
  logic [DEPTH-1:0][WIDTH-1:0] mem_array;
  ...
  ##0 (1'b1, mem_array[0] = data_in);
...
... 
##1  (1'b1, mem_array[1] = data_in);
  ...
  |-> 
  ...
  ##0 data_out == mem_array[0];
  ##1 data_out == mem_array[1];
  ...
  ; endproperty

However, when I check the witness waveform, the mem_array appears as a 1D array, not as the 2D array I intended.

Any ideas on how to correctly define and reference a 2D non-deterministic array inside a property in formal verification?

I would appreciate any suggestions or best practices to resolve this issue.