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2073 Results

  • Resolving Metastability Issues for Multi-clock SoC Environment for I2C

    This article aims to resolve metastability issues for multi-clock designs by noting the clock domains and the synchronization required for crossing the clock domains. The example SoC has an 8-bit simple Microcontroller and a Memory Module with a clock differently aligned (multi-clock) to the I2C Master and Slave. Leading to issues regarding metastability that needed to be resolved using synchronizers – currently two flip-flops using a closed-loop solution for sending and receiving clock domains.

  • Big Data for Verification – Inspiration from Large Language Models

    ChatGPT, one of the most prominent Large Language Models (LLMs), has proven it is capable of human-level knowledge by passing multiple exams with faded colors: Warton’s MBA exam with a B, the US Medical Licensing Exam at the threshold, and four law school courses at the University of Minnesota with a C+. Individually, they are definitely not the best an excellent professional can achieve, but still are a good demonstration of LLMs’ strengths of appearing universally knowledgeable.

  • Simulating UVMF Code on Windows

    In this session, you will learn how to use the UVMF Build/Compile/Run script on Windows.

  • Simulating UVMF Code on Windows

  • Generating UVMF Code on Windows

    In this session, you will learn how to use the generation scripts on Windows to produce UVMF testbench source.

  • Generating UVMF Code on Windows

  • Installing Python on Windows

    In this session, you will learn how to install Python on a Windows system for use with UVMF scripts.

  • Installing Python on Windows

  • UVMF Build/Compile/Run Script Introduction

    In this session, you will be introduced to the capabilities and use of the UVMF Build/Compile/Run script.

  • UVMF Build/Compile/Run Script

  • Register Adapters, Predictors, and Tests

  • Register Adapters, Predictors and Tests

    In this session, you will learn how to use register model adapters, predictors, and tests in UVMF.

  • Register Model Generation and Replacement

    In this session, you will learn how to produce a UVM register model, applying it to a UVMF testbench.

  • Register Model Generation and Replacement

  • Register Model Generation and Integration

    In this session, you will be introduced to the generation of a register model as part of a UVMF environment.

  • Register Model Generation and Integration

  • UVM Framework Release 2023.1

    General Updates: Added BASE_T type parameter to scoreboard classes to allow insertion of user base class. Added supper.xxx_phase calls to classes with BASE_T type parameter.

  • UVM Framework

    In this track you will learn more about UVM Framework and how it that provides a reusable UVM methodology and code generator for rapid testbench generation.

  • UVMF -All

    UVMF v2023.4_2 Generator Updates: Replaced new with factory create for construction of broadcasted transaction from monitor.

  • Verification Data Analytics with Machine Learning

    Verification is data-and computation-intensive, making it an ideal field for ML applications. Advancements in ML have offered many opportunities to accelerate verification workflow, improve verification quality, and automate verification execution. However, being a data-centric method, ML has also elevated data to become the most crucial factor of ML success.

  • Verification Data Analytics with Machine Learning

    This whitepaper provides an overview on the importance of data to ML, the available data for verification, and the existing applications of ML in verification. It reveals that data itself may dictate applicable ML models. Machine learning has demonstrated great potential in verification. However, attention should be paid to generalizing and scaling the models to ensure their success in a production environment.

  • The UVM Factory Revealed - Part 2

    This is a follow up to last week’s high-level post on the UVM Factory . Now let’s get technical! Here are the SystemVerilog Object-Oriented Programming concepts behind the factory.

  • Epilogue: 2022 Study Summary and Key Findings

    This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. I opened this blog series with a  Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.

  • FPGA Functional Verification Trend Report - 2022

    This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2022 Wilson Research Group study.

  • IC/ASIC Functional Verification Trend Report - 2022

    This report examines the trends in functional verification for integrated circuits (ICs) and application-specific integrated circuits (ASICs) as identified in the 2022 Wilson Research Group study.