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Using the Register Layer
Session - May 25, 2021 by Tom Fitzpatrick
This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses.
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Using the Register Layer
Resource (Slides) - May 25, 2021 by Tom Fitzpatrick
Using the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.
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Register-Based Testing
Session - May 25, 2021 by Tom Fitzpatrick
This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage.
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Register-Based Testing
Resource (Slides) - May 25, 2021 by Tom Fitzpatrick
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The Three Witches Preventing Glitch Nightmares on CDC Paths
Resource (Technical Paper) - May 18, 2021 by Ping Yeung
At the RTL, we focus on identifying the clock domains and CDC paths by recognizing the CDC structures and schemes. At the gate-level, CDC paths with multiplexer or combinational logic are often prone to glitch defects that can be introduced during the synthesis, timing, and power optimization process. If CDC verification is only done at RTL, such glitch defects can easily be missed and lead to costly post-silicon chip failure.
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Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Resource (Technical Paper) - May 12, 2021 by Michael Fingeroff - Siemens EDA
Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet next-generation machine learning hardware demands at the edge.
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Formal 101 – Setting Up & Optimizing Constraints
Session - May 10, 2021 by Mark Eslinger
In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.
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Setting Up & Optimizing Constraints
Resource (Slides) - May 10, 2021 by
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Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Webinar - May 04, 2021 by Jacob Wiltgen
In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.
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Low Power Considerations for Verification
Webinar - Apr 29, 2021 by Rick Koster
Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.
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Formal 101 – Basic Abstraction Techniques
Session - Apr 21, 2021 by Jin Hou
In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.
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A Methodology for Comprehensive CDC+RDC Analysis
Resource (Slides) - Apr 20, 2021 by Kurt Takara
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
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A Methodology for Comprehensive CDC+RDC Analysis
Webinar - Apr 20, 2021 by Kurt Takara
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
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A Guide to QVIP Workflow and Debug for PCIe®
Webinar - Apr 08, 2021 by Akshay Sarup
In this session, you will learn the step-by-step workflow to integrate Questa Verification IP (QVIP) - PCIe® into a testbench including key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.
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Easy Test Writing with a Proxy-driven Testbench
Webinar - Apr 06, 2021 by Ray Salemi
In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.
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Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Resource (Technical Paper) - Mar 31, 2021 by
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Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Resource (Technical Paper) - Mar 31, 2021 by
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Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
Resource (Slides) - Mar 31, 2021 by Michael Fingeroff - Siemens EDA
This workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology.
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Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
Seminar - Mar 31, 2021 by Michael Fingeroff - Siemens EDA
This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator.
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Functional Debug: Verification and Beyond
Webinar - Mar 31, 2021 by Hanan Moller
In this session, we will discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.
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Making Your DPI-C Interface a Fast River of Data
Webinar - Mar 31, 2021 by Rich Edelman
This session will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Webinar - Mar 31, 2021 by Progyna Khondkar
This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
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Functional Debug: Verification and Beyond
Webinar - Mar 31, 2021 by Hanan Moller
In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
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Bringing Reset and Power Domains Together – Confronting UPF Instrumentation
Webinar - Mar 31, 2021 by Abdul Moyeen
This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
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Making Your DPI-C Interface A Fast River Of Data
Resource (Slides) - Mar 31, 2021 by Rich Edelman
DPI-C is a powerful way to integrate C code with SystemVerilog. The interface is a simple function or task call, identical to a normal SystemVerilog function or task call. This paper will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.