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Making Your DPI-C Interface A Fast River Of Data
Resource (Technical Paper) - Mar 31, 2021 by Rich Edelman
SystemVerilog DPI-C enables functional verification teams to leverage C code for modeling, checking and utility functions. The simple "C" style call interface allows fast adoption and easy integration. This paper explains the workings of the integration and provides data type mapping examples and some hints on optimizing the calls for maximum performance.
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“Bounded Proof” Sign-Off with Formal Coverage
Webinar - Mar 31, 2021 by Joe Hupcey
In this session, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Webinar - Mar 31, 2021 by Abdul Moyeen
This session specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Slides) - Mar 31, 2021 by Abdul Moyeen
There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design structures where there are more than one asynchronous set/reset controlling a flop. Then there can be scenarios involving data transfer between two such flops. Another matter of concern is if the output of such flops is used as reset further down the design.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Technical Paper) - Mar 31, 2021 by Abdul Moyeen
There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design features where there is more than one asynchronous set/reset controlling a flop. This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Technical Paper) - Mar 31, 2021 by Abdul Moyeen
Reset domain Crossing has emerged into a major and un-avoidable design step in modern ASIC design flows. In any Digital design, Reset Domain Crossing (RDC) is essentially a structure where a signal crosses over from one reset domain to another reset domain. In this paper we will try to look at the problem structurally and propose a strategy to reach a conclusion where we face such design structures.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Resource (Slides) - Mar 31, 2021 by Progyna Khondkar
Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Resource (Technical Paper) - Mar 31, 2021 by Progyna Khondkar
This paper distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
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Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation
Resource (Slides) - Mar 31, 2021 by Abdul Moyeen
The Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design.
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Bringing Reset Domains and Power Domains Together - Confronting Issues Due to UPF Instrumentation
Resource (Technical Paper) - Mar 31, 2021 by Abdul Moyeen
This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
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Functional Debug: Verification and Beyond
Resource (Slides) - Mar 31, 2021 by Hanan Moller
In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
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I Didn’t Know Visualizer Could Do That
Webinar - Mar 30, 2021 by Rich Edelman
In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
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Preventing Glitch Nightmares on CDC Paths
Webinar - Mar 26, 2021 by Ping Yeung
As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
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Applying Big Data to Next-Generation Coverage Analysis and Closure
Webinar - Mar 26, 2021 by Darron May
In this session, we will explore new ways of visualizing coverage data from different verification platforms – including simulation, emulation, FPGA and virtual prototyping and formal verification – to facilitate analytical navigation, and applying advanced analytics, including data mining and machine learning, to help your team identify functional coverage holes and effectively mobilize your verification team to reach coverage closure like never before.
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The Life of a SystemVerilog Variable
Webinar - Mar 26, 2021 by Dave Rich
This session presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
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Preventing Glitch Nightmares on CDC Paths
Resource (Slides) - Mar 26, 2021 by Ping Yeung
As we are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals will undoubtedly reduce reliability and lead to potential silicon failures. Hence, CDC verification is essential at both the RTL and the gate-level. Previously, we have been focusing on preventing and catching glitches on the data multiplexing paths.
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Bounded Proof Sign-Off with Formal Coverage
Resource (Technical Paper) - Mar 26, 2021 by Joe Hupcey
In this paper, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
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Applying Big Data to Next-Generation Coverage Analysis and Closure
Resource (Slides) - Mar 26, 2021 by Darron May
Coverage closure remains the biggest functional verification challenge in our industry. This two-hour technical presentation will establish the need for a next-generation collaborative verification platform, providing enterprise-wide team-based shared coverage analytics and collaborative verification process integration, including lifecycle management integration.
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Bounded Proof Sign-Off with Formal Coverage
Resource (Technical Paper) - Mar 26, 2021 by Joe Hupcey
When using formal verification on large DUTs, after solving an initial set of provable assertions, it is common to have some remaining assertions which are not proven -- or disproven -- in the course of the analysis. Even though formal couldn’t conclusively verify the expected behavior, the DUT behaviors recorded up until the analysis halted still provides meaningful information.
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The Life of a SystemVerilog Variable
Resource (Technical Paper) - Mar 26, 2021 by Dave Rich
Some of the most common issues are how and when variables get initialized, how concurrent threads interact with the same variable, and how certain variable lifetimes interact with other SystemVerilog features in terms of performance considerations. This paper presents a background on the different categories of variable lifetimes, what their intended use models are, and how improper usage can be corrected.
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The Life of a SystemVerilog Variable
Resource (Slides) - Mar 26, 2021 by Dave Rich
In software programming, lifetime is defined by when and from where a variable is available for access. This is particularly important when there are multiple process threads with lifetimes of their own trying to access the same variable. A variable becomes a symbolic name for a particular range of memory locations allocated to a specific data type.
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Preventing Glitch Nightmares on CDC Paths: The Three Witches
Resource (Slides) - Mar 26, 2021 by
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Preventing Glitch Nightmares on CDC Paths: The Three Witches
Resource (Technical Paper) - Mar 26, 2021 by
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ModelSim to Questa - Productivity Features
Webinar - Mar 25, 2021 by Jonathan Craft
In this session, you will gain an understanding of the differences between the ModelSim and Questa simulators and will be introduced to the advanced verification techniques and methodology necessary for design and verification of high-end FPGA and ASIC.
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Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Webinar - Mar 25, 2021 by Ray Salemi
This session introduces `pyuvm`, a Python implementation of IEEE Spec 1800.2. It discusses the Python tricks used to implement UVM features such as the factory, FIFOs, and config_db.