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1771 Results

  • UVM Framework Release 2021.3

    General Updates: General bug fixes and documentation updates Generator Updates: Added C data types for Mathworks® integration flow

  • Sequential Logic Equivalence Checking

    In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

  • SLEC Introduction

    In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.

  • SLEC for Design Optimization

    In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.

  • SLEC for Bug Fix / ECO

    In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.

  • SLEC for Low Power Clock Gating

    In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.

  • SLEC for Safety Mechanism

    In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.

  • Leveraging Advancements in UPF 3.1 for Effective Design and Verification

    In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

  • Part I: Introduction to PCIe® Gen 6

    In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

  • Introduction to UVM

    This session gives an overview of UVM, the motivation and benefits, and technical highlights.

  • Introduction to UVM | Japanese

  • Introduction to UVM

  • UVM "Hello World" | Japanese

  • UVM "Hello World"

    This session walks through a short, simple example to get you started with UVM.

  • UVM "Hello World"

  • Connecting Env to DUT

  • Connecting Env to DUT | Japanese

  • Connecting Env to DUT

    This session explains how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database.

  • Connecting Components | Japanese

  • Connecting Components

  • Connecting Components

    This session explains the phases of a UVM component, focusing on how to use the build and connect phases.

  • Introducing Transactions

    This session explains how to use transactions to communication between a sequencer and a driver in UVM.

  • Introducing Transactions | Japanese

  • Introducing Transactions

  • Sequences and Tests

    This session explains how to create sequences of transactions, sequences of sequences, and how to start a sequence from a test.