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UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
Article - Mar 02, 2022 by Espen Tallaksen - EmLogic
Verification takes half of a typical FPGA project’s development time. It is possible to significantly reduce this time with only minor adjustments and no extra cost while dramatically increasing the ability to reuse testbench components. An FPGA design’s architecture – from the top to the microarchitecture – is critical for both the FPGA quality and the development time. The same is true of the testbench.
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Equivalence Checking for FPGA
Webinar - Feb 25, 2022 by Martin Rowe
In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.
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Achieving High Defect Coverage for Safety Critical and High Reliability Designs
Webinar - Feb 22, 2022 by Lee Harrison
In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets.
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‘The Dog Ate my RTL’ Doesn’t Work Anymore
Webinar - Feb 15, 2022 by Joe Hupcey
In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.
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‘The Dog Ate my RTL’ Doesn’t Work Anymore
Resource (Slides) - Feb 15, 2022 by Joe Hupcey
In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.
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Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
Article - Feb 02, 2022 by Verification Horizons
Despite being a common requirement, handling hardware resets in a verification environment has always been beset by a host of challenges, including: Despite being a common requirement, handling hardware resets in a verification environment has always been beset by a host of challenges, including: Reset behavior has to be propagated to all testbench components. All UVM components such as driver monitor and scoreboard should be capable of reacting to the reset (i.e., they should be made reset aware). All pending sequences already scheduled by the test should be removed from all sequencers and virtual sequencers. Once the system comes out of reset the traffic should be re-generated to the DUT.
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Introduction to Questa Lint and CDC for Designers
Resource (Slides) - Jan 25, 2022 by Mathew Yee
In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.
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Introduction to Questa Lint and CDC for Designers
Webinar - Jan 25, 2022 by Mathew Yee
In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.
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Odds and Ends
Resource (Verification Horizons Blog) - Jan 14, 2022 by Ray Salemi
This final blog post in the series discusses odds and ends that may have gotten little attention in the blog posts or may not have been invented when the blog post was written.
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Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal
Webinar - Dec 20, 2021 by Joe Hupcey
In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, validating low power clock gating and more.
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Logging in PYUVM
Resource (Verification Horizons Blog) - Dec 14, 2021 by Ray Salemi
This blog post provides a brief overview of logging and compares it to UVM reporting. Then it discusses logging in pyuvm .
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Courtines and COCOTB Testbench Code
Resource (Tarball) - Dec 14, 2021 by Ray Salemi
This Git repository contains the working code used as examples in the "Python for Verification" Verification Horizons Blog posts.
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Exhaustive Trust & Security Verification by Leveraging Emerging Standards
Resource (Recording) - Dec 08, 2021 by John Hallman
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Exhaustive Trust & Security Verification by Leveraging Emerging Standards
Resource (Slides) - Dec 08, 2021 by John Hallman
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Validation of Complex Safety Architectures
Webinar - Nov 18, 2021 by Vedant Garg
This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.
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The UVM Factory
Resource (Verification Horizons Blog) - Nov 17, 2021 by Ray Salemi
The pyuvm implements the UVM factory as it is described in the specification, removing elements that complicated the factory because of SystemVerilog typing.
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Formal 101 – Data Independence and Non-Determinism Made Easy
Session - Nov 11, 2021 by Jin Hou
In this session, we will show how with a little design knowledge and forethought on your part, you can leverage these two principles to cut down your formal analysis to a matter of minutes vs. hours.
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Data Independence and Non-Determinism Made Easy
Resource (Slides) - Nov 11, 2021 by
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How to Finish Faster with Hierarchical CDC+RDC Methodologies
Resource (Slides) - Nov 02, 2021 by Kurt Takara
In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.
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Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies
Webinar - Nov 02, 2021 by Kurt Takara
In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.
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The Configuration Database in PYUVM
Resource (Verification Horizons Blog) - Oct 27, 2021 by Ray Salemi
Now we turn our attention to some of the UVM’s utilities and how we use them in Python. The first of these is the UVM configuration database.
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Improving Your SystemVerilog Language and UVM Methodology Skills
Track - Oct 27, 2021 by Chris Spear
If you are building complex testbenches with SystemVerilog and UVM, this series is for you. The series dives into many aspects of these two areas, to give you deeper insight about how to apply the language and methodology on your projects. Whether you are new to SystemVerilog and UVM, or have been writing code for many years, take a fresh look at the fundamentals and learn some new ideas and approaches.
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Total Recall - What to Look for in a Memory Model Library
Article - Oct 26, 2021 by Mark Peryer
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IC/ASIC Functional Verification Trend Report - 2020
Resource (Technical Paper) - Oct 22, 2021 by
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CDC Philosophy: The existential questions of constraints, waivers, and truth
Webinar - Oct 12, 2021 by Kurt Takara
In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.