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1771 Results
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CDC Philosophy: The existential questions of constraints, waivers, and truth
Resource (Slides) - Oct 12, 2021 by Kurt Takara
In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.
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TLM 1.0 in pyuvm
Resource (Verification Horizons Blog) - Oct 01, 2021 by Ray Salemi
We’ll examine pyuvm’s implementation TLM 1.0 using simple producer/consumer examples. First, we’ll handle blocking operations.
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Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Session - Sep 28, 2021 by Mark Eslinger
In this session, we will show you how to use IEEE standard property checking code (SVA) and off-the-shelf formal tools to quickly and exhaustively verify data transport through the DUT matches the specification.
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Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Resource (Slides) - Sep 28, 2021 by
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Improving Initial RTL Quality
Webinar - Sep 15, 2021 by Chris Giles
This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
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Improving Initial RTL Quality | Japanese
Resource (Japanese Translation Slides) - Sep 15, 2021 by Chris Giles
This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
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Improving Initial RTL Quality
Resource (Slides) - Sep 15, 2021 by Chris Giles
This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
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Questa AutoCheck - Advanced Linting
Demo - Sep 14, 2021 by Mark Eslinger
This session demonstrates the Questa AutoCheck advanced linting tool and how it can be used with Questa Lint and Questa X-Check for a full suite of RTL checks without a testbench.
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Questa X-Check: Identify "X" Issues
Demo - Sep 14, 2021 by Mark Eslinger
This session demonstrates how the Questa X-Check tool can identify X issues without any simulation, complementing Questa Lint and AutoCheck for a full suite of RTL checks.
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Questa Lint - Find and Fix RTL Issues
Demo - Sep 14, 2021 by Tom Carlstedt-Duke
This session demonstrates how Questa Lint is used to find and fix RTL issues without a testbench or constraints.
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Questa CDC Verification
Demo - Sep 14, 2021 by Kurt Takara
This session demonstrates the Questa CDC Verification comprehensive solution to clock-domain verification.
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Python and the UVM
Resource (Verification Horizons Blog) - Sep 09, 2021 by Ray Salemi
An introduction to pyuvm and how we can use it to write UVM code on top of cocotb .
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Questa Reset Domain Crossing (RDC)
Demo - Sep 02, 2021 by Atul Sharma
This session will demonstrate the Questa RDC Verification Solution and will introduce key features in RDC GUI, like RDC Matrix, Directive Window and other debug features.
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What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Article - Sep 01, 2021 by Tom Fitzpatrick
Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping.
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Digital Thread, Digital Twin, and IC Development
Article - Sep 01, 2021 by Ray Salemi
In October of 2020, the Air Force challenged Aerospace and Defense industry to adopt the suggestions presented in the 2018 Digital Engineering Strategy. The document, named " There is No Spoon: The New Digital Acquisition Reality ”, warns that aircraft design and deployment must embrace “the digital trinity” of Digital Engineering and Management, Agile Software Development, and Open Architecture.
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Addressing the Trends and Challenges of Automotive IC Development
Article - Sep 01, 2021 by Ann Keffer
Developers of ICs, systems, and even vehicles are seeing some pretty significant shifts in the automotive industry. Recent estimates forecast that 50% of a vehicle’s Bill of Materials (BOM) will be electronics and electronic systems by the year 2030. Smart mobility is the root cause as the market demands features such as lane keep, adaptive cruise control, and emergency brake assist to name a few.
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Deploying HLS in a DO-254/ED-80 Workflow
Article - Sep 01, 2021 by Tammy Reeve - Patmos Engineering Services
The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.
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Hardware-Assisted Verification Through the Years
Article - Sep 01, 2021 by Jean-Marie Brunet
A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA.
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Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Article - Sep 01, 2021 by Jean-Marie Brunet
Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars.
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Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Article - Sep 01, 2021 by Stephen Bailey
In a 2010 inaugural issue of the report from the UK High Performance Computing Special Interest Group (HPC-SIG), the following statement resonated with a large number of companies and research institutions that were using HPC technology. "Over the past decade there has been a revolution in High Performance Computing spearheaded by a movement away from using expensive traditional proprietary supercomputers to systems based on relatively inexpensive commodity off-the-shelf systems." [1]
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"Hug the Debug" – Before It’s Too Late
Article - Sep 01, 2021 by Sumit Vishwakarma
Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry.
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Questa Visualizer Adds Coverage Analysis to the Platform
Article - Sep 01, 2021 by Yara Esam - Siemens EDA
Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs.
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Verifying a DDR5 Memory Subsystem
Article - Sep 01, 2021 by Kamlesh Mulchandani
The latest technologies and applications often demand more speed and performance. With the advancement in technologies such as multi-core CPUs and GPUs, the need for faster data processing is becoming a bottleneck for system performance. Applications such as Machine Learning and Data Centers rely upon high performance and lower latency. These applications need a memory that can offer high speed, better performance, high density, lower latency, and data integrity.
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Expediting Simulation Turn-around Time with Incremental Build Flow
Article - Sep 01, 2021 by Neil Johnson
Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use to constantly validate progress. Whether the result is a failed compile, passing simulation or anything in between, the sooner you get that result, the sooner you get to the next step and closer you get to your ultimate objective: passing silicon.
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Standards Participation at Siemens EDA
Article - Sep 01, 2021 by Dave Rich
All of us are involved with standards every day whether we realize it or not. From the day we are born, we interact with standards. In the US, a baby receives a standardized health assessment score called Apgar after 1 minute. You are weighed and measured to standards. You wear clothes sized to standards. Eventually, you learn to read and write according to some culturally accepted standards.