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Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification

Resource (Slides (.PDF)) - May 21, 2024 by Chris Giles

Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.
Functional Monitoring: From Lab to In-Life

Resource (Slides (.PDF)) - May 21, 2024 by Fady Abushahla - Siemens EDA

In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.
Navigating Reset Domain Crossings to Safety in Complex SoCs

Resource (Verification Horizons Blog) - May 21, 2024 by Reetika - Siemens EDA

As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management blocks, and DSP cores are proliferating. This surge necessitates a shift towards intricate power and performance management strategies, often incorporating several asynchronous and soft resets.
Beyond Speed: Unlocking Productivity in Simulation and Debug

Resource (Slides (.PDF)) - May 21, 2024 by Moses Satyasekaran

Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.
Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

Resource (Slides (.PDF)) - May 21, 2024 by Austin Mam

This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.
The New Leader in Verification IP: Questa + Avery Solutions

Resource (Slides (.PDF)) - May 21, 2024 by Kamlesh Mulchandani

Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
From Chaos to Order: Using Continuous Integration for Hardware Functional Verification

Paper - May 13, 2024 by Dr. Abdelouahab Ayari

In recent years, continuous integration and development have become crucial in organizing software development cycles. As a result, it has also become a way to streamline hardware flow, especially with the increased complexity of chips and SoCs. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.
From Chaos to Order: Using Continuous Integration for Hardware Functional Verification

Resource (Paper (.PDF)) - May 13, 2024 by Dr. Abdelouahab Ayari

Continuous integration plays an important role in organizing the hardware flow and making integration seamless, easy, and trackable using the ability of running multiple jobs in parallel it is capable of accelerating the workflow. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.
Without Objection: Touring the uvm_objection Implementation - Uses and Improvements

Resource (Paper (.PDF)) - May 13, 2024 by Rich Edelman

This paper will explain uvm_objections implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.
Without Objection: Touring the uvm_objection Implementation - Uses and Improvements

Paper - May 13, 2024 by Rich Edelman

The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that “isn't done yet.” For example, an objection can prevent a process from finishing until some other process agrees. uvm_objections are sometimes overused and are always misunderstood. This paper will explain the implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.
On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

Paper - May 10, 2024 by Farhad Ahmed

Reset tree checks should be viewed thoroughly before RDC analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction.
On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

Resource (Paper (.PDF)) - May 10, 2024 by Farhad Ahmed

This paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.
Developing “Safe” AI Hardware

Conference - May 07, 2024 by Shaumik Ganguly - Continental

In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.
Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Conference - May 07, 2024 by Suma Ramanand - Nokia

In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.
Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

Conference - May 07, 2024 by Ariel Ansbacher - Veriest

In this session you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.
Extraction of VC File for Physical Macro From Top VC File

Conference - May 07, 2024 by Nirav Patel - Arm

A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.
Improving Simulation Performance Utilizing the Visualizer Profiler

Conference - May 07, 2024 by George Lloyd - Arm

In this session you will learn how Visualizer Profiler was used to identify areas for improvement within Arm VIP components and how these issues were addressed, reducing simulation time that were achieved due to these optimizations.
Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches

Conference - May 07, 2024 by Espen Tallaksen - EmLogic

In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).
Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend

Conference - May 07, 2024 by Mihajlo Katona - Veriest

In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method.
New AI Horizons in Static & Formal Verification

Resource (Recording) - Apr 24, 2024 by Dan Yu
New AI Horizons in Static & Formal Verification

Resource (Slides (.PDF)) - Apr 24, 2024 by Dan Yu
Optimizing FPGA Equivalence Checking for A&D Designs

Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Urish
Driving Efficient Execution with Continuous Integration

Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Campbell
Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

Resource (Slides (.PDF)) - Apr 24, 2024 by Dr. Jonathan Graf
osmosis Aerospace and Defense 2024

Conference - Apr 24, 2024 by John Hallman

osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.