- Matthew Ballance - Mentor Graphics
Design and verification have historically been driven by domain-specific languages. Reuse guidelines have long existed for reuse of a description within the same language or methodology, but do not exist for reusing a description across languages. An Accellera standardization effort around a Portable Stimulus Specification standard, and the existence in the industry of portable stimulus tools that can retarget an abstract test specification to multiple environments, provide a driver for the creation of such guidelines. This paper provides guidelines for structuring SystemVerilog stimulus and coverage specifications to maximize reuse with a portable stimulus specification language.
Reuse in verification has been a goal as long as verification has existed as a unique discipline. Languages such as SystemVerilog and methodologies such as the Universal Verification Methodology (UVM) have greatly helped automation and reuse in transaction-oriented simulation and accelerated-simulation verification environments. Bringing test-creation automation and reuse to an even broader set of environments and executions platforms is the goal of the Accellera Portable Stimulus Specification (PSS) standard.
The goal of this standard, as summarized by Figure 1, is to enable multiple user constituencies to use and reuse the same specification of test stimulus, expected results, and coverage goals across a variety of platforms, including simulation, emulation, and prototype.
The developing Portable Stimulus Specification is fundamentally a declarative language that includes data structures, constraints, coverage-specification features, and graphs – a formally-analyzable specification of test procedure. Like other standards in the verification space, the developing Portable Stimulus Specification benefits from the experience of multiple vendors and users with tools that already exist in this space.
Propagation and adoption of new language standards benefit heavily from the ability to reuse existing descriptions, and the Portable Stimulus Specification is no different. Given that the bulk of verification today is done using SystemVerilog, it makes sense to see what elements of a SystemVerilog description can be easily and reliably reused in a Portable Stimulus Specification description. This paper explores the SystemVerilog constructs most easily reused in a Portable Stimulus Specification, and provides coding guidelines to make reuse simple and reliable.
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Read the entire Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse technical paper.
DVCon US 2016