System verilog constraint

Hi Guyz,

I need help in writing constraint for a 3x3 matrix which is of bit type and i need to constraint it in such a manner, that sum of all elements of 3x3 matrix is 6.
Note. I am not able to do sum on this two dimensional matrix within constraints as .sum is applicable to single dimension.
Share your codes please.

I am still a student so don’t know if this is a good solution. I tried a lot of things like matrix.sum with (item.sum) but that didn’t work. In the end the good old brute force method worked. The code is given below:

constraint c1{(matrix[0][0]+matrix[0][1]+matrix[0][2]
                      +matrix[1][0]+matrix[1][1]+matrix[1][2]
                      +matrix[2][0]+matrix[2][1]+matrix[2][2]
) == 6;}

When using the brute force method, there is one equation where the operands are expanded to the widest operand’s width.m In your case, the operand 6 is a decimal signed integer whose width is 32-bits.

As mentioned in the link I provided earlier, the sum() reduction method evaluates the sum as a function call that returns a result with the same width as each array element. It doesn’t consider the width of the rest of the operands outside the method when determining the width of the result.

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