Topics tagged systemverilog

Topic	Replies	Views	Activity
Clock Inference for Embedded concurrent assertion SystemVerilog SystemVerilog , assertion , SVA , embedded-concurrent-assertion	2	55	November 25, 2024
How can a task return a Queue? SystemVerilog SystemVerilog , task , return-data , functions-in-system-verilog	9	7875	November 26, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	21	4954	November 25, 2024
Write a constraint to generate the pattern 1234554321 SystemVerilog SystemVerilog , systemverilog-constraint	3	141	November 25, 2024
Embedding concurrent assertions in procedural code SystemVerilog SystemVerilog , assertion , SVA	2	329	November 25, 2024
Regarding UVM_QUEUE and their methods UVM OVM , SystemVerilog , UVM	2	64	November 25, 2024
Question on Sequence concatenation '##' SystemVerilog SystemVerilog , assertion , SVA	1	41	November 24, 2024
2D array constraint randomization SystemVerilog SystemVerilog , 2D-array-SystemVerilog-randomization	18	5797	November 24, 2024
Legal declaration of concurrent assertion statement SystemVerilog SystemVerilog , assertion , SVA , concurrent-assertion	2	32	November 23, 2024
Write constraint for an integer array with 10 elements such that exactly 3 of them are same and rest are unique SystemVerilog SystemVerilog , unique-array	9	2214	November 20, 2024
How using Functional Coverage we can find out, if there is any missing functionality in the DUT? SystemVerilog SystemVerilog	4	858	November 20, 2024
Constraining OCM base addresses SystemVerilog SystemVerilog , constraint-randomization	1	52	November 19, 2024
Constrain block to allocate dedicated non over-lapping address range space for 16 masters SystemVerilog SystemVerilog , systemverilog-randomization	7	1828	November 19, 2024
Question on Fork join with case statement SystemVerilog SystemVerilog , fork-join	3	94	November 18, 2024
Array vs queue SystemVerilog SystemVerilog	3	1258	June 23, 2015
Cannot use svSetScope to call DPI-C function/task in C++ SystemVerilog SystemVerilog , dpi-c , C	1	33	November 10, 2024
D Flip Flop UVM Test bench UVM SystemVerilog	2	65	November 8, 2024
Method/function overloading SystemVerilog SystemVerilog	15	17879	November 7, 2024
How to padd number of zeros to the front of the randomized data SystemVerilog SystemVerilog , constraint-randomization	1	71	November 7, 2024
.triggered and .matched of SVA sequence in multi clock property SystemVerilog SystemVerilog , assertion , SVA	4	120	November 6, 2024
System verilog constraint for transaction SystemVerilog SystemVerilog , systemverilog-constraint	3	358	November 6, 2024
SV Functional Coverage Coverage SystemVerilog , Coverage	6	169	November 6, 2024
How to set up drain time properly? UVM SystemVerilog	2	110	November 5, 2024
Array.sum method is not working as expected SystemVerilog SystemVerilog	3	331	November 4, 2024
Popping Queue elements as sequence_expr SystemVerilog SystemVerilog , assertion , SVA-Assertion	7	161	November 2, 2024
Implementing Read on Clear (RC) register SystemVerilog SystemVerilog	4	62	October 28, 2024
Constrain sum of elements in an array SystemVerilog SystemVerilog , constraint-randomization , Dynamic-Array	24	28802	October 27, 2024
Seek suggestions for following SV constraints SystemVerilog SystemVerilog , constraint-randomization , randomization , systemverilog-constraint	6	436	October 27, 2024
Pattern Generation SystemVerilog SystemVerilog , constraint-randomization	12	3892	October 27, 2024
Signal written by more than one continuous statement SystemVerilog SystemVerilog , questasim , Polymorphism , BFM , sv-interfaces	4	2878	October 24, 2024