I rechecked the sequence and sequencer memory allocation, all are correct but still i am getting null pointer error, i posted the code below please check. the error is not showing the perfect file name also.
// Code your testbench here
// or browse Examples
import uvm_pkg::*;
include "uvm_macros.svh" include “interface.sv”
include "sequence_item.sv" include “sequencer.sv”
include "driver.sv" include “agent.sv”
include "sequence.sv" include “environment.sv”
`include “test.sv”
module test_bench();
logic clk,tclk;
logic resetn;
encoding_8bit_to_10bit DUT(.clk(clk),.resetn(resetn));
encode_inter intf(clk,tclk,resetn);
initial begin
uvm_config_db #(virtual encode_inter)::set(null,"*","interface",intf);
clk=0;
tclk=0;
resetn=0;
#10;
resetn=1;
end
initial begin
run_test(“test”);
end
always
#1 clk=~clk;
always
#8 tclk=~tclk;
initial begin
$dumpfile(“dump.vcd”);
$dumpvars(0, test_bench);
end
endmodule
///////////////////////////////////////////////////////////////TEST////////////////////////////////////////////////////
class test extends uvm_test;
`uvm_component_utils(test)
environment env;
int a,b;
function new(string name=“test”,uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env= environment::type_id::create(“env”,this);
endfunction
function void end_of_elaboration_phase(uvm_phase phase);
$display(“PRINTING THE TOPOLOGY”);
uvm_top.print_topology();
endfunction
virtual task run_phase(uvm_phase phase);
test_sequence seq=test_sequence::type_id::create(“seq”);
phase.raise_objection(this);
$display(“RUN_PHASE OF TEST STARTED”);
a=env.agt.seqr.a;
$display(“VALUE OF A=%0d”,a);
b=seq.b;
$display(“VALUE OF B=%0d”,b);
seq.start(env.agt.seqr);
$display(“RUN_PHASE OF TEST CONNECTED”);
phase.drop_objection(this);
endtask
endclass
///////////////////////////////////////////sequence//////////////////////////////////////////
class test_sequence extends uvm_sequence;
`uvm_object_utils(test_sequence)
sequence_item req;
int b;
function new(string name=“test_sequence”);
super.new(name);
b=20;
endfunction
virtual task body();
repeat(10);
begin
req = sequence_item::type_id::create(“req”);
wait_for_grant();
assert(req.randomize());
send_request(req);
wait_for_item_done();
end
endtask
endclass
/////////////////////////////////////////////////environment//////////////////////////////////////
class environment extends uvm_env;
`uvm_component_utils(environment)
agent agt;
function new(string name=“environment”, uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agt=agent::type_id::create(“agt”,this);
endfunction
endclass
////////////////////////////////////////////////agent//////////////////////////////////////////
class agent extends uvm_agent;
`uvm_component_utils(agent)
driver drv;
sequencer seqr;
function new(string name=“agent”,uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
drv=driver::type_id::create(“drv”,this);
seqr=sequencer::type_id::create(“seqr”,this);
endfunction
function void connent_phase(uvm_phase phase);
super.connect_phase(phase);
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction
endclass
////////////////////////////////////////////driver////////////////////////////////////////////
class driver extends uvm_driver#(sequence_item);
`uvm_component_utils(driver)
virtual encode_inter intf;
function new(string name=“driver”,uvm_component parent=null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
// Get interface reference from config database
super.build_phase(phase);
if(!uvm_config_db#(virtual encode_inter)::get(this, “”, “interface”, intf)) begin
`uvm_error(“”, “uvm_config_db::get failed”)
end
endfunction
task run_phase(uvm_phase phase);
#10;
forever
begin
seq_item_port.get_next_item(req);
drive();
seq_item_port.item_done();
end
endtask
task drive();
@(posedge intf.tclk);
for(int i=0;i<8;i++)
begin
@(posedge intf.clk);
intf.DATA<=req.start_data;
@(posedge intf.clk);
intf.DATA<=req.raw_data1;
@(posedge intf.clk);
intf.DATA<=req.raw_data2;
@(posedge intf.clk);
intf.DATA<=req.raw_data3;
@(posedge intf.clk);
intf.DATA<=req.raw_data4;
@(posedge intf.clk);
intf.DATA<=req.raw_data5;
@(posedge intf.clk);
intf.DATA<=req.raw_data6;
@(posedge intf.clk);
intf.DATA<=req.sync_data;
@(posedge intf.clk);
end
endtask
endclass
//////////////////////////////////////////////////sequencer////////////////////////////////
class sequencer extends uvm_sequencer#(sequence_item);
`uvm_component_utils(sequencer)
int a;
function new(string name=“sequencer”,uvm_component parent=null);
super.new(name,parent);
a=10;
endfunction
endclass