Operators in sv

SystemVerilog
1

Hi Team ,

module test;
  reg signed [8:0] sin_hall2;

     initial begin
       sin_hall2 = -9'd4 ;
       $display( "Comparison unsigned : %b ", sin_hall2 > 9'd1 );
       $display( "Comparison cast     : %b ", sin_hall2 > $signed(9'd1) );
     end
endmodule

In the above example i am trying to understand but missing something . Please help

Here is my understanding :

  1. sin_hall2>9’d1:
    In this sin_hall2 = -(9’sb11111_1100) > 9’b00000_0001;
    After 2’s complement
    9’b00000_0100 >9’b00000_0001 /// result is true -->1
  2. **sin_hall2 > $signed(9’d1)
    -(9’sb11111_1100) >9’sb00000_0001;
    9’b00000_0100 >9’b00000_0001 /// result is true -->1 —>but simulator gives 0 as output

Please provide some inputs on how these operations signed and unsigned comparison works in this context
Please help me to get the difference of $signed(9’d1) and 9’d1 and 9’sd1 with respect to operators .

Thanks in Advance

Regards,
Mechanic

2

You are doing an extra 2-complement. The signedness of an operand does not change the bits, just its interpretation for certain operations like relations and extension.
9’d4 is a 9-bit unsigned value 9’b00000_0100. When you apply unary minus (2’s complement) it becomes the 9-bit unsigned value 9’b11111_1100, which is 508 decimal. That get stored in th 9-bit signed variable sin_hall2. The bits do not change, but it is now interpreted as the signed value -4. It would not matter if you had used 9'sd4 instead.

When comparing two values, both must be signed to do a signed comparison. Since 9'd1 is unsigned, the first comparison is 508 > 1, which is true (1’b1).

In the second comparison, you could write $signed(9'd1), signed'(9'd1), or 9'sd1. Any of those would make both operands signed, so the operation is now a signed comparison. -4 is not greater than 1, the result is 1’b0.

3

Hi Dave

Thank you

Could you please provide some examples for the below statement

I have tried the below example with extended form please correct me if i miss something

module test;
  logic signed [3:0] a;
  logic signed [7:0] b,c;
  initial begin 
    a=7;
    $display("value of a is %b  ",a);
    b= a<<1;
    $display("b=%b", b);
    c= signed'(a<<1);
    $display("c=%b",c);
  end 
endmodule

//Operation expanded
//b= a<<1;
// 0000_0111<<1 ///first sign extended then shifting
//0000_1110

//c= signed’(a<<1);
//c= signed’(1110) // first shifting then sign extended
//c= 1111_1110

4

That is correct. Another way to think of this is converting from signed to unsigned, or from unsigned to signed does not modify any bits of a value. It will change how certain operations behave, producing different value results. Your original example shows the difference in relational operatos, and this next example show the difference in extension.