Topics tagged System-Verilog

Topic	Replies	Views	Activity
How to calculate TON, TOFF, Time period of a signal UVM UVM , System-Verilog , delay-uvm_components , uvm-testbench-verification	1	279	November 29, 2023
This simple Question was asked in Interview. Why is associative arrays preferred over dynamic arrays in scoreboard? SystemVerilog SystemVerilog , assertion , scoreboard , System-Verilog , associative-array , accessing-the-associative-array-elements	3	453	November 29, 2023
SVA to check whether a signal is stable between 2 events SystemVerilog SystemVerilog , System-Verilog , SVA , Assertions-stable , systemverilogassertionSVA , A-few-questions-on-SVA	7	542	November 29, 2023
Constraint to get the previous Randomized Value SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	2	311	November 28, 2023
Automatic task in Fork join_none SystemVerilog SystemVerilog , System-Verilog , system-verilog-fork-join_none--delay	2	264	November 20, 2023
Randomizing struct members - why do I see this error? SystemVerilog SystemVerilog , System-Verilog , structure	1	210	November 8, 2023
System Verilog Object Construction SystemVerilog SystemVerilog , System-Verilog	1	151	November 7, 2023
Create a 3-byte queue SystemVerilog SystemVerilog , System-Verilog , Queues	3	316	October 31, 2023
How to override a value driven from the TB in a test SystemVerilog SystemVerilog , System-Verilog , illegal-class-assignment , bit-slice-in-force-syntax , signal_force	1	259	October 30, 2023
System verilog function argument output SystemVerilog SystemVerilog , System-Verilog , FunctionArgument	4	347	October 30, 2023
Randomization Question UVM UVM , System-Verilog , uvm-sv-constraints	4	386	October 16, 2023
Delete more than one entry in System verilog queue SystemVerilog SystemVerilog , System-Verilog	1	200	October 6, 2023
Conditional assertion inside a module scope SystemVerilog SystemVerilog , assertion , System-Verilog	8	396	October 6, 2023
Semaphore put method question SystemVerilog SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys	1	184	October 2, 2023
Error: <file> in protected region SystemVerilog SystemVerilog , error , System-Verilog , vopt	1	202	October 2, 2023
System Verilog coverage Coverage Coverage , System-Verilog , systemverilog-coverage-cross , Coverage-bins	5	483	September 25, 2023
Null object error Coverage Coverage , System-Verilog , Null-Object-Access , coverage-UVM-module-class	1	329	September 16, 2023
Blocking or non-blocking statement (= vs. <=) SystemVerilog SystemVerilog , System-Verilog , assignment	3	467	September 13, 2023
Getting syntax error, need solution SystemVerilog SystemVerilog , System-Verilog	1	153	September 13, 2023
Free netlist simulations UVM UVM , System-Verilog , RTL-coverage , GLS-simulation , NETLIST	0	123	September 4, 2023
Asynchronous FIFO Assertions For Verifying Data Pushed and Popped SystemVerilog SystemVerilog , assertion , System-Verilog , FIFO-UVM-ConstrainedRandom , system-verilog-assertions-past-stable , Assertions-clock	1	405	September 1, 2023
Assign statement SystemVerilog SystemVerilog , System-Verilog , Dave-Rich , Chris-Spear	3	310	August 31, 2023
How to achieve fork-join_none and fork join_any functionality using fork-join SystemVerilog SystemVerilog , System-Verilog , fork-join_any , fork-join_none , fork-join , threads	4	409	August 28, 2023
Constraints SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	4	439	August 28, 2023
What is a pipelined driver in AXI3? UVM UVM , System-Verilog , axi , UVM-DRIVER-INTERFACE , coverage-UVM-module-class , uvm-pipeline	1	199	August 23, 2023
Post Synthesis Simulation error, unable to find ports due to flattening 2D array ports to 1D SystemVerilog SystemVerilog , System-Verilog , post-synthesis-verification	2	166	August 23, 2023
Proper Use of Semaphores in Parallel Threads SystemVerilog SystemVerilog , semaphore , System-Verilog , fork_join	2	251	August 17, 2023
How to code the dist statement with array in the constraint SystemVerilog SystemVerilog , System-Verilog	8	945	August 10, 2023
How to take variable in array index? SystemVerilog SystemVerilog , System-Verilog	1	356	August 1, 2023
Passing array as an argument (packed vs unpacked, dynamic vs fixed) SystemVerilog SystemVerilog , System-Verilog , passing-arguments-by-reference-to-task , 2Darray , packed-arrays-unpacked-arrays-array-conversion	3	430	August 1, 2023