Topics tagged System-Verilog

Topic	Replies	Views	Activity
Assertion to check Clock pattern SystemVerilog assertion , System-Verilog , SVA	1	414	January 31, 2024
Connecting inout real to real data type SystemVerilog UVM , Coverage , assertion , System-Verilog , SVA	1	433	January 30, 2024
Inheritance of clock for sequence used as event control SystemVerilog SystemVerilog , System-Verilog , SVA	4	332	January 16, 2024
Randcase usage to get all possible values of logic (four state) data type SystemVerilog SystemVerilog , UVM , System-Verilog	2	266	January 14, 2024
Inheritance use extended class to inject error SystemVerilog SystemVerilog , System-Verilog	4	276	January 14, 2024
Coverpoint for dist Coverage SystemVerilog , Coverage , System-Verilog	1	478	January 2, 2024
System verilog constraints - Random number generation SystemVerilog SystemVerilog , System-Verilog	4	809	January 1, 2024
Evaluation of following Multi-clocked sequence SystemVerilog SystemVerilog , assertion , System-Verilog	2	209	December 27, 2023
Conditional inline constraint SystemVerilog System-Verilog , constraints	4	644	December 20, 2023
Null instance encountered when dereferencing OVM OVM , System-Verilog , mixed-UVM-OVM	1	362	December 17, 2023
Training material - Broken links SystemVerilog SystemVerilog , System-Verilog	0	248	December 16, 2023
Output of the code SystemVerilog SystemVerilog , System-Verilog , for-loop , Dave-Rich	5	595	December 12, 2023
SystemVerilog $monitor SystemVerilog SystemVerilog , System-Verilog	1	431	December 4, 2023
Waiting for positive edge of the clock using wait() SystemVerilog SystemVerilog , System-Verilog , question-wait--posedge-clock	2	1150	November 30, 2023
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	1	723	November 29, 2023
How to calculate TON, TOFF, Time period of a signal UVM UVM , System-Verilog , delay-uvm_components , uvm-testbench-verification	1	511	November 29, 2023
This simple Question was asked in Interview. Why is associative arrays preferred over dynamic arrays in scoreboard? SystemVerilog SystemVerilog , assertion , scoreboard , System-Verilog , associative-array , accessing-the-associative-array-elements	3	959	November 29, 2023
SVA to check whether a signal is stable between 2 events SystemVerilog SystemVerilog , System-Verilog , SVA , Assertions-stable , systemverilogassertionSVA , A-few-questions-on-SVA	7	874	November 29, 2023
Constraint to get the previous Randomized Value SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	2	488	November 28, 2023
Automatic task in Fork join_none SystemVerilog SystemVerilog , System-Verilog , system-verilog-fork-join_none--delay	2	557	November 20, 2023
Randomizing struct members - why do I see this error? SystemVerilog SystemVerilog , System-Verilog , structure	1	342	November 8, 2023
System Verilog Object Construction SystemVerilog SystemVerilog , System-Verilog	1	235	November 7, 2023
Create a 3-byte queue SystemVerilog SystemVerilog , System-Verilog , Queues	3	594	October 31, 2023
How to override a value driven from the TB in a test SystemVerilog SystemVerilog , System-Verilog , illegal-class-assignment , bit-slice-in-force-syntax , signal_force	1	439	October 30, 2023
System verilog function argument output SystemVerilog SystemVerilog , System-Verilog , FunctionArgument	4	760	October 30, 2023
Randomization Question UVM UVM , System-Verilog , uvm-sv-constraints	4	580	October 16, 2023
Delete more than one entry in System verilog queue SystemVerilog SystemVerilog , System-Verilog	1	320	October 6, 2023
Conditional assertion inside a module scope SystemVerilog SystemVerilog , assertion , System-Verilog	8	757	October 6, 2023
Semaphore put method question SystemVerilog SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys	1	358	October 2, 2023
Error: <file> in protected region SystemVerilog SystemVerilog , error , System-Verilog , vopt	1	505	October 2, 2023

Assertion to check Clock pattern

SystemVerilog

assertion , System-Verilog , SVA

1

414

January 31, 2024

Connecting inout real to real data type

SystemVerilog

UVM , Coverage , assertion , System-Verilog , SVA

1

433

January 30, 2024

Inheritance of clock for sequence used as event control

SystemVerilog

SystemVerilog , System-Verilog , SVA

4

332

January 16, 2024

Randcase usage to get all possible values of logic (four state) data type

SystemVerilog

SystemVerilog , UVM , System-Verilog

2

266

January 14, 2024

Inheritance use extended class to inject error

SystemVerilog

SystemVerilog , System-Verilog

4

276

January 14, 2024

Coverpoint for dist

Coverage

SystemVerilog , Coverage , System-Verilog

1

478

January 2, 2024

System verilog constraints - Random number generation

SystemVerilog

SystemVerilog , System-Verilog

4

809

January 1, 2024

Evaluation of following Multi-clocked sequence

SystemVerilog

SystemVerilog , assertion , System-Verilog

2

209

December 27, 2023

Conditional inline constraint

SystemVerilog

System-Verilog , constraints

4

644

December 20, 2023

Null instance encountered when dereferencing

OVM

OVM , System-Verilog , mixed-UVM-OVM

1

362

December 17, 2023

Training material - Broken links

SystemVerilog

SystemVerilog , System-Verilog

0

248

December 16, 2023

Output of the code

SystemVerilog

SystemVerilog , System-Verilog , for-loop , Dave-Rich

5

595

December 12, 2023

SystemVerilog $monitor

SystemVerilog

SystemVerilog , System-Verilog

1

431

December 4, 2023

Waiting for positive edge of the clock using wait()

SystemVerilog

SystemVerilog , System-Verilog , question-wait--posedge-clock

2

1150

November 30, 2023

Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector

Coverage

Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array

1

723

November 29, 2023

How to calculate TON, TOFF, Time period of a signal

UVM

UVM , System-Verilog , delay-uvm_components , uvm-testbench-verification

1

511

November 29, 2023

This simple Question was asked in Interview. Why is associative arrays preferred over dynamic arrays in scoreboard?

SystemVerilog

SystemVerilog , assertion , scoreboard , System-Verilog , associative-array , accessing-the-associative-array-elements

3

959

November 29, 2023

SVA to check whether a signal is stable between 2 events

SystemVerilog

SystemVerilog , System-Verilog , SVA , Assertions-stable , systemverilogassertionSVA , A-few-questions-on-SVA

7

874

November 29, 2023

Constraint to get the previous Randomized Value

SystemVerilog

SystemVerilog , System-Verilog , constraint-randomization

2

488

November 28, 2023

Automatic task in Fork join_none

SystemVerilog

SystemVerilog , System-Verilog , system-verilog-fork-join_none--delay

2

557

November 20, 2023

Randomizing struct members - why do I see this error?

SystemVerilog

SystemVerilog , System-Verilog , structure

1

342

November 8, 2023

System Verilog Object Construction

SystemVerilog

SystemVerilog , System-Verilog

1

235

November 7, 2023

Create a 3-byte queue

SystemVerilog

SystemVerilog , System-Verilog , Queues

3

594

October 31, 2023

How to override a value driven from the TB in a test

SystemVerilog

SystemVerilog , System-Verilog , illegal-class-assignment , bit-slice-in-force-syntax , signal_force

1

439

October 30, 2023

System verilog function argument output

SystemVerilog

SystemVerilog , System-Verilog , FunctionArgument

4

760

October 30, 2023

Randomization Question

UVM

UVM , System-Verilog , uvm-sv-constraints

4

580

October 16, 2023

Delete more than one entry in System verilog queue

SystemVerilog

SystemVerilog , System-Verilog

1

320

October 6, 2023

Conditional assertion inside a module scope

SystemVerilog

SystemVerilog , assertion , System-Verilog

8

757

October 6, 2023

Semaphore put method question

SystemVerilog

SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys

1

358

October 2, 2023

Error: <file> in protected region

SystemVerilog

SystemVerilog , error , System-Verilog , vopt

1

505

October 2, 2023