SystemVerilog $monitor

module test;
  
  int a=10;
  
  initial
    begin
      for (int i=0; i<10; i++)
        begin
          $monitor("monitor=%0d",a);
          a=i+10;
          $strobe("strobe=%0d",a);
          $display("***********");
        end
    end
endmodule

in this code why the monitor is not hit by 10 times as per expectation

In reply to Berlin:

https://verificationacademy.com/forums/systemverilog/monitor-does-not-get-printed#reply-108116