Randcase usage to get all possible values of logic (four state) data type

SystemVerilog
, ,
1

Hi All,

I am trying to use randcase to display all values of logic randomly.
But not able to get Z (high impedence) value.
May I know how to get z, means, for what operation we will get an output of Z?

===============================
program p1;
class parent;
rand logic payload;

function void post_randomize();
  randcase
  1: begin
  	 	payload = payload & 1;
     end
  1: begin
  		payload = !payload & 1;
  	 end
  1: begin
  		payload = payload & 'hx;
     end
  1: begin
  		payload = payload & 'hz;
     end
  endcase
  	$display("logic %0d",payload);
endfunction

endclass

parent c1;
initial begin
c1 = new;
repeat (6) begin
c1.randomize();
end
end
endprogram

output

xcelium> run
logic 1
logic x
logic 0
logic 0
logic 0
logic 0

2

Not sure what your intention is, but recall that SV randomization handles only 2-state, i.e. result of randomize() shall be 2-state (not X/Z). Your observation on X after post_randomize() is due to bitwise &, LRM has the below table:

image

3

Okay, Thank you for the useful infomation