Clocking Block in System Verilog

SystemVerilog
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1

How to take an asynchronous signal from clocking block?

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correct me if i’m wrong,
I think clocking blocks will help in synchronous access to signals,
if you are passing the interface somewhere we have define modports, and mention the signal which you want to access asynchronusly,
like :

define ADDR_WIDTH 32
`define DATA_WIDTH 32
`define NO_OF_SLAVES 7
// Code your design here
interface apb_if(input logic pclock);
  logic                         presetn;
  logic [`ADDR_WIDTH - 1 : 0]   paddr;
  logic [`DATA_WIDTH - 1 : 0]   pwdata;
  logic [`DATA_WIDTH - 1 : 0]   prdata;
  logic                         pwrite;
  logic                         pready;
  logic [`NO_OF_SLAVES - 1 : 0] psel_x;
  logic                         penable;
  logic                         pslverr;
  
  bit has_checks = 1;
  bit has_coverage = 1;
  
  clocking m_drv_cb@(posedge pclock);
     default input #1 output #0;
     output psel_x;
     output penable;
     output pwrite;
     output paddr;
     output pwdata;
     input  pready;
     input  prdata;

  endclocking : m_drv_cb

//---------------------------------------------------------------------
  modport m_drv_mp(clocking m_drv_cb,input presetn);
endinterface : apb_if

in above code,
signal presetn will be asynchronous rest all the signals will be synchronous.