Dynamic Sampling

SystemVerilog
,
1

Hi All,
I have an interface consisting of following 1-bit wide logic type signals

// "RD" stands for Redundant lane which is used if there exists connectivity issue with respective non-RD lane
TxDATASB , TxCKSB , TxDATASBRD , TxCKSBRD ,  
RxDATASB , RxCKSB , RxDATASBRD , RxCKSBRD

During module instantiation the respective Tx* signal of die0 is connected to respective Rx* signal of die1.
Similarly respective Tx* signal of die1 is connected to respective Rx* signal of die0.

I am currently working on the phy monitor where there is a Tx fsm as well as Rx fsm.
In the post-reset state each die sends a pattern on TxDataSB as well as TxDATASBRD while also transmitting clock on TxCKSB and TxCKSBRD.
Initially within the phy monitor I use these 4 combinations of data and clock

 // Within Tx fsm for both die0 and die1
 forever@( negedge TxCKSB ) begin
      tx_datasb_cksb.push_back( TxDataSB );
      tx_datasbrd_cksb.push_back( TxDataSBRD ) ;     
 end
 forever@( negedge TxCKSBRD ) begin
      tx_datasb_cksbrd.push_back( TxDataSB );
      tx_datasbrd_cksbrd.push_back( TxDataSBRD );
 end

 // Within Rx fsm for both die0 and die1
 forever@( negedge RxCKSB ) begin
      rx_datasb_cksb.push_back( RxDataSB );
      rx_datasbrd_cksb.push_back( RxDataSBRD ) ;
 end
 forever@( negedge RxCKSBRD ) begin
      rx_datasb_cksbrd.push_back( RxDataSB );
      rx_datasbrd_cksbrd.push_back( RxDataSBRD );
 end

There is a possibility that there is an connectivity issue with the non-RD Tx and Rx lane which would cause the pattern to be observed on strictly RD lane ( vice-versa is also possible )
Eg: Pattern is received only on RxDataSBRD using RxCKSBRD as clock.

After transmission of the pattern each die sends a 4-bit result message to the partner to know on which lane was the pattern received. There are 4 possibilities

CKSB sampling DATASB = Result[0]  # 1: Detected; 0: Not detected
CKSBRD sampling DATASB = Result[1] # 1: Detected; 0: Not detected
CKSB sampling DATASBRD = Result[2] # 1: Detected; 0: Not detected
CKSBRD sampling DATASBRD = Result[3] # 1: Detected; 0: Not detected

IF (Result[3:0] == XXX1):   // Highest priority for non-RD lane
Sideband = (DATASB/CKSB)
ELSE IF (Result[3:0] == XX10):
Sideband = (DATASB/CKSBRD)
ELSE IF (Result[3:0] == X100):
Sideband = (DATASBRD/CKSB)
ELSE IF (Result[3:0] ==1000): // Lowest priority for RD lane
Sideband = (DATASBRD/CKSBRD)

Now depending on result[3:0] the Tx and Rx fsm should only utilize the respective Data and Clock combination for further communication in the following states

Note : It’s possible that result[3:0] of die0 could be different than result[3:0] of die1

My question is regarding implementation of this dynamic sampling in the phy monitor.

  1. Assume for die0, result[3:0] == 4’b1111 so the Rx fsm for die0 should use CKSB sampling DATASB ( as they have highest priority )
    In this case the phy monitor should operate as ::
 // Within Rx fsm for die0
 forever@( negedge RxCKSB ) begin
      rx_datasb.push_back( RxDataSB );
 end

// Transmitter of die1 will now only transmit on DATASB using CKSB as clock
// Within Tx fsm for die1
 forever@( negedge TxCKSB ) begin
      tx_datasb.push_back( TxDataSB );
 end
  1. Assume for die1, result[3:0] == 4’b1000 so the Rx fsm for die1 should use CKSBRD sampling DATASBRD
    In this case the phy monitor should operate as ::
 // Within Rx fsm for die1
 forever@( negedge RxCKSBRD ) begin
      rx_datasb.push_back( RxDataSB );
 end

// Transmitter of die0 will now only transmit on DATASBRD using CKSBRD as clock
// Within Tx fsm for die0
 forever@( negedge TxCKSBRD ) begin
      tx_datasb.push_back( TxDataSBRD );
 end

Any suggestions on how should I implement the dynamic sampling using 4-bit result ?