Assertion to check Clock pattern

SystemVerilog
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Hi All,
I am trying to write SVA to check following scenario

Transmitter should send 128 iterations of clock repair pattern (16 clock cycles followed by 8 cycles of low)

Assume clock is 1GHz i.e 1ns with initially either tri-stated or low with 50% duty cycle.
The intention can be divided into 3 scenarios ::

  1. Transmitter drives 16 clock cycles from initial 'Z/0

  2. After 16 clock cycles there should be 8Tclks ( 8ns ) of low

  3. There are 128 such iterations of 1 followed by 2

My approach ::

//  To check 8 cycles low 
 sequence seq;
   realtime t1,t2;
  @(negedge txck) ( 1[*16] , t1 = $realtime ) |-> @(posedge txck ) (1,t2 = $realtime ) ##0 ( ( t2 - t1 ) == 8ns );
 endsequence

[Q1] ‘seq’ has a limitation that there is an attempt on each negedge whereas the expectation is to trigger an attempt only after the 16th consecutive negedge of clock

Consider a case where initially txclk is 'Z/ 0 .
So when the transmitter drives 16 clocks, the 16th attempt would have an issue ( using leading clock as @( posedge clk) ) due to lack of 17th posedge.

[Q2] I could check time between 2 posedges , however I am not clear on how can I check that there were indeed 16 clock cycles in each iteration ?

[Q3] How do I check (3) i.e there are 128 iterations of (1) followed by (2) ?

2

Your question is very similar to this other question at