Conditional inline constraint

SystemVerilog
,
1

I am trying to randomize a variable in an object using inline constraint based on a condition. the variable of the condition is not a member of the object, but is a variable in the parent class from where randomization is called. The issue i am facing is that, while randomizing, the conditional statement is not honored, and inline constraint is not applied. Code snippet below.

class rand_obj;
  rand bit test_value;
endclass 

class test;
  bit cond_flag = 1;
  rand_obj obj;
  //obj created
  assert(obj.randomize() with
{
 if(**cond_flag**) obj.test_value == 0;
else obj.test_value == 1;
}
endclass

In this above code, i am getting random values for test_value, while i am expecting for every time it should generate test_value == 0, since cond_flag is set.

Can someone please point me out the issue here.

Thanks,
Debashis

2

Maybe you’ve something more in actual code. As such this looks fine. Maybe you are looking for local:: prefix that’s useful if you have cond_flag is in your obj_class as well.

3

You need to show us exactly how randomize() gets called. It would help to show a minimally complete example.

4

Thanks… I went back to the code, and found issue in how “cond_flag” was set.
In this example, for the sake of simplicity i set the cond_flag in this class itself, but in real code, it was from a command line argument, which was actually not getting set properly.

5

Thanks Dave. Found the issue with command line argument not setting “cond_flag” properly. For the sake of simplicity, i set the “cond_flag” in the class itself, but in real code it was from command line. Issue resolved now.
I Will try to show a minimally complete code next time.