Waiting for positive edge of the clock using wait()

SystemVerilog
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1

is it possible to wait for positive edge of clock using wait(), something like wait((posedge clk).triggered).

1 Like
2

In reply to Rahulvala:

In reply to Aman551:
There are two ways to do it.
first by using always_ff block:

always_ff @(posedge clk) begin
// Your code here
end

second using forever block :

forever begin
wait(clk == 1'b1);
// Your code here
end

These generative answers from Rahulvala contain a lot of incorrect information and will be removed. always_ff is not an answer to the question. And the forever loop will hang the simulation once the clock becomes 1.

wait() is a level sensitive construct. If you want to wait for an edge, you need two of them in a sequence.

wait(clk==0) wait(clk==1)

This is close to what @(posedge clk) without handling X states.

3

In reply to dave_59:

In reply to Rahulvala:
These generative answers from — contain a lot of incorrect information and will be removed.

Thanks, please do ASAP - the value of such tech forums is quickly lost with bot-generated-wrong-responses. It clutters the threads and readers need to identify the needle in hay soon. Please note this forum comes up often on Google search results and serves as a reference for years for many of us, so let’s all do what we can to maintain the quality here, please.