Output of the code

SystemVerilog
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1

Hi,

Can you help me to find why this code gives output as 0.I am not able to understand the output because it has to be executed serially so the output of the display must be 20.


module test;
  int a;  
  initial begin
    for(int i = 0;i<20;i++)begin
      a = a++;
    end
    $display("a = %0d",a);
  end
endmodule
2

In reply to m_v:

module test;
  int a;  
  initial begin
    for(int i = 0;i<20;i++)begin
       a++;
      end
    $display("a = %0d",a);
  end
endmodule

this will gives you the expected answer.

3

In reply to Nandakumari:

Hi,yes this will work but i want to understand why that code is giving the output 0.

Thanks.

4

In reply to m_v:

because always value of a is 0 here.
first loop: a = 0; then value of a is incremented but not assigned; =>still value of a is zero this repeats.
if assign a = ++a ; this assigns incremented value and works as you expected.
hope you understood.

5

In reply to Nandakumari:

Okay. I got you but why incremented value is not assigned? can you explain.

Thanks

6

In reply to m_v:

In reply to Nandakumari:
Okay. I got you but why incremented value is not assigned? can you explain.
Thanks

I believe that’s a race condition. As per LRM:

SystemVerilog includes the C increment and decrement assignment operators ++i, --i, i++, and i–.
These do not need parentheses when used in expressions. These increment and decrement assignment
operators behave as blocking assignments.
The ordering of assignment operations relative to any other operation within an expression is undefined. An
implementation can warn whenever a variable is both written and read-or-written within an integral
expression or in other contexts where an implementation cannot guarantee order of evaluation

Atleast one simulator does warn on such usage.

HTH