Inheritance use extended class to inject error

SystemVerilog
,
1

Hi All,

Here is the below code:

module p1;
  class parent;
    rand bit [3:0] sa,da,payload[8];
    bit 	 [3:0] crc;
  
  function void cal_crc;
    crc = (sa ^ da ^ payload.xor);
  endfunction
  
    function void post_randomize();
      $display("parent: CRC output %0d",crc);
      $display("sa %0d da %0d",sa,da);
    endfunction
    
  endclass
  
  class child extends parent;
   rand bit error; 
  function void cal_crc;
    super.cal_crc();
    if (error) begin
    	crc = ~crc;
    	$display("child : CRC output %0d",crc);
    end
  endfunction
  endclass
  
  child c1;
  initial begin
    c1 = new;
    repeat (1) begin
    c1.randomize();
    c1.cal_crc();
    end
  end
endmodule

=================

output of the code

parent: CRC output 0
sa 3 da 14
child : CRC output 8

If error is set, then parent crc should be complement.
Lets say if crc is 'h01, complement of this must be 'hFE.
but parent crc is always zero, I am not able to see non zero value of crc in parent class.
I could not understand the issue, may I know the reason?

Thank You,

2

You call randomize() (which calls post_randomize() ) before you call cal_crc().

3

Thank you for the reply. Sorry I did not understand,
You means this,

repeat (1) begin
c1.cal_crc();
c1.randomize();
end

4

No, try calling calc_crc inside post_randomize()

5

Thank you Srini and Dave.
It worked