System verilog constraints - Random number generation

SystemVerilog
,
1

//write a constraint to generate 100 bit variable for 2 cases : 1) 7 bits are 1 at random places 2) 7 bits are random at continous places .

2

In reply to Ajit Gangad:

case : 1
rand bit [99:0] count ;

constraint c_100_bit { $countones(count) == 7 ; }

can you explain 2nd case little bit more

1 Like
3

In reply to Ajit Gangad:

https://verificationacademy.com/forums/systemverilog/i-want-constrained-random-10-bit-such-there-wont-be-7-consecutive-0s-or-1s.-can-someone-suggest-anything-thanks-advance.#reply-96719

5

Thanks @dyno . for the first part of question . 2nd part of question is to generate continuous stream of 1’s (7 bits continuously )at random places of 100 bit variable.

Anyway I have written below SV code for the same and working as expected . Any other solution from your side is welcome .

class c; 
 
   rand bit[99:0]a;
   rand int unsigned  position ;
 
  constraint c0{ 
  position inside {[0:92]};
  }

  constraint c1{
     $countones(a) == 7;
     foreach(a[i]) {
     if(i>=position && i < position +7 )  a[i]==1;
     else a[i]==0;
     }
}
endclass

module top_constraints; 
       c c1;
       initial begin 
        c1=new(); 
        repeat(100) begin 
         c1.randomize();
         $display ("%b",c1.a) ;
        end 
        
         $stop; 
        end  
 endmodule    

Output-
 #0011111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
# 0000000000000000000000000001111111000000000000000000000000000000000000000000000000000000000000000000
# 0000000000000000000000000000000000000000000000000001111111000000000000000000000000000000000000000000
# 0001111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111110000
# 0000000111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
# 0111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
# 0000000000000000000000111111100000000000000000000000000000000000000000000000000000000000000000000000
6

Thanks @dave_59 . I am able to solve 2nd part of question with mentioned links .
https://verificationacademy.com/forums/systemverilog/i-want-constrained-random-10-bit-such-there-wont-be-7-consecutive-0s-or-1s.-can-someone-suggest-anything-thanks-advance.#reply-96719