I want to constrained random 10 bit such that there won't be 7 consecutive 0s or 1s. Can someone suggest anything ? Thanks in advance

SystemVerilog
,
1

Let’s say there is one rand 10-bit variable named data. Now I want to make sure there won’t be 7 consecutive 0s or 1s. Can someone suggest me how can I constraint in such way ?

2

In reply to jigar123:

You might want to look at this or this for ideas.

3

In reply to dave_59:

parameter width = 7;

constraint c_data
{
    foreach(data[i]) 
    {
        (i < data.size() - width) -> !(data[i+:width] inside {'0,'1};
    }
}
4

In reply to dave_59:

Hi Dave, can you help explain your constraint ? The right hand side of implication operator. If the data is declared as bit do we need inside operator?



class tb;
  rand bit [9:0] data;
  // I want to constrained random 10 bit such that there won't be 7 consecutive 0s or 1s. Can someone suggest anything ?
 parameter width = 7;
 
constraint c_data
{
    foreach(data[i]) 
    {
      (i < $size(data) - width) -> !(data[i+:width] inside {'0,'1});
                                       }
}
      // i=0 ; (0 < 10 - 7) -> !data[0+:7] should not be inside 0 or 1
      // i=1 ; (1 < 10 - 7 ) -> !data[1+:7] should not be inside 0 or 1
      // i=2 ; (2 < 10 -7) -> !data[2+:7] should not be inside 0 or 1
  
endclass

module ab;
  tb t1;
  initial begin
    t1= new();
  
  if (!t1.randomize()) begin
    $display ("Randomize Error"); end
  
    $display ("%b",t1.data);
  end
endmodule