How to override a value driven from the TB in a test

SystemVerilog
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1

I have a 10 bit DUT input wire ‘in’, that is being driven from the TB with value 0 by default, as shown below.


module my_tb;

   mydut dut (
     // other connections
     .in(0));

endmodule

In my test, I would like to override this value with a random value in the configure phase


class my_test extends base_test;
   `uvm_component_utils(my_test)

  bit [9:0] rand_val;

  function new(string name = "my_test", uvm_component parent = null);
    super.new(name,parent);
  endfunction

  virtual task configure_phase(uvm_phase phase);
    std::randomize(rand_val);
    repeat(1) @(posedge clk);
    my_tb.dut.in[9:0] = rand_val;
  endtask

endclass

  1. The line my_tb.dut.in[9:0] = rand_val; gives me the error: “Non reg type is not valid on the left hand side of this assignment”

  2. If I do assign my_tb.dut.in[9:0] = rand_val;, I get the error: “Bit select or part select cannot be used on the left hand side of this assignment”

  3. If I do force my_tb.dut.in[9:0] = rand_val;, I get the error: “Class data is not allowed in non-procedural context.”

How can I drive an input wire to the DUT from my test?

2

In reply to vk7715:

I recommend creating a UVC agent and driving the value like you would any other agent.