Topics tagged systemverilog

Topic	Replies	Views	Activity
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	640	April 23, 2024
How to pass delay through a variable in assertion SystemVerilog SystemVerilog	7	2047	April 23, 2024
Empty bin warning for disabled cover point Coverage SystemVerilog , Coverage	1	56	April 19, 2024
Elaboration time constant for enumerated type.num() SystemVerilog SystemVerilog	2	44	April 18, 2024
Parameter type in interface SystemVerilog SystemVerilog , interface	1	55	April 16, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	998	April 16, 2024
Illegal range in part select SystemVerilog SystemVerilog	10	4819	April 16, 2024
APB state operation SystemVerilog SystemVerilog	0	54	April 15, 2024
NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED SystemVerilog SystemVerilog , virtual-interface-scoreboard-uvm	5	373	April 15, 2024
Constraint array SystemVerilog SystemVerilog , systemverilog-constraint	2	106	April 12, 2024
Function New Constructor UVM SystemVerilog , UVM	1	79	April 11, 2024
How do I avoid using #0 in an interface monitor SystemVerilog SystemVerilog , UVM	3	80	April 10, 2024
How the within syntax is working in SVA SystemVerilog SystemVerilog , assertion , SVA	7	2225	April 10, 2024
System Verilog Fine grain Process SystemVerilog SystemVerilog	2	95	April 9, 2024
Backdor access without using RAL model SystemVerilog SystemVerilog	3	79	April 8, 2024
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	6352	April 7, 2024
Understanding a Bug in the Distribution Constraint SystemVerilog SystemVerilog	4	96	April 8, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	83	April 7, 2024
Best Practice for Unit Tests Extending Chip-Level Tests UVM SystemVerilog , Inheritance	1	74	April 6, 2024
Solve before constraint used with implication operator SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	7	107	April 6, 2024
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	52025	April 5, 2024
Passing variables to a subroutine on sequence match SystemVerilog SystemVerilog , assertion , SVA	2	111	April 5, 2024
LRM :: "Assertion evaluation does not wait on or receive data back from any attached subroutine" SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	1	48	April 5, 2024
Modeling dynamic delay range via subroutine SystemVerilog SystemVerilog , Modeling-dynamic-delay-range-via-subroutine	5	523	April 2, 2024
Constraint solve order SystemVerilog SystemVerilog , constraint-randomization	1	117	April 3, 2024
UVM run_test Method UVM SystemVerilog	2	68	April 3, 2024
Is there any way to set a global solve...before? SystemVerilog SystemVerilog , constraint , solve-before	1	84	April 3, 2024
Input port cannot be driven SystemVerilog SystemVerilog	8	11931	April 3, 2024
3 unique arrays - constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	1	121	April 3, 2024
Manual seeding as an alternative to calling new() repeatedly SystemVerilog SystemVerilog , constraint-randomization , randomization	4	74	April 2, 2024