Manual seeding as an alternative to calling new() repeatedly

SystemVerilog
, ,
1

Hi All,
I remember reading a SV thread raised a few months ago where the intention was to achieve rand behavior using randc variable ( unfortunately I am unable to find it currently )
One possible solution shared in the thread was to call new() before each call to randomize

  class base;    
    randc bit [2:0] a;    
  endclass  
  
  base b_h;
  
  initial begin    
    repeat(9) begin
     b_h = new();     
     if( b_h.randomize() )  $display("Success with %0p",b_h.a);      
    end      
  end

Is there a possible alternative to achieve the same non-cyclic output using Manual seeding ( via function srandom ) or by using function set_randstate ?

2

Call new() and re-seeding via srandom have the same effect on random number generation.

You should only call set_randstate() with a value retrieved from get_randstate() It acts as a guard for random stability.

3

I did try both ways using random seeds on tools

  1. Using_srandom
  2. Using_get_randstate_N_set_randstate

However the output is still random cyclic for the first eight randomization.
Any suggestions ?

1 Like
4

Apparently the cyclic sequence of a randc variable is state stored in a class object not connected to the seeding. The LRM says:

The permutation sequence for any given randc variable is recomputed whenever the constraints change on that variable or when none of the remaining values in the permutation can satisfy the constraints. The permutation sequence shall contain only 2-state values.

5

Dave,
So the only possible alternative to the code at the top would be to use constraint the randc variable to give non-cyclic output ?

Unfortunately when testing on edaplayground only 1 tool gives me the expected output ( edalink )