How to do a backdoor access of a register without using RAL model in System verilog Testbench and also where is the HDL path defined in SV Testbench ?
“Backdoor” access means directly reading/writing a register in a non-time-consuming manner without needed to go through the normal operation of the design (the frontdoor).
SystemVerilog provides a number of mechanisms to do this using hierarchical references, $readmem, and PLI access via string pathnames. The UVM RAL uses the latter method.
If you are not using the standard UVM as your testbench, I can not answer your question without knowing how your testbench is set up.
Thanks for your reply @dave_59 . This was an interview question to do backdoor access of a register without using RAL module .
so i want to know which module or which component in the testbench do we set the HDL path to access register through backdoor access and how exactly backdoor access can be done from sequences or from anywhere we want to do backdoor access.
If you can explain this with an example or with syntax to set HDL path , it would be really helpful .
Otherwise you are asking me to re-write the UVM RAL.