Constraint solve order

SystemVerilog
,
1

I happened to come across this constraint example on the internet.

There is a signal wdata[63:0] representing data-bus
There is a signal wstrb[7:0] representing strobe/valid byte of the data-bus
Constraint is when a valid byte is present in wdata, it has to be either 8’b11111111 or 8’b10101010
Write a SV code/constraint to generate suitable transactions

class Example;
  rand bit[7:0] wstrb;
  rand bit[63:0] wdata;
  rand bit [7:0] valid_byte;

  constraint c0{valid_byte inside {8'b11111111, 8'b10101010};}
  
  constraint c2{foreach( wstrb[i])
                wstrb[i] inside {0,1};};
  
  constraint c1{foreach(wstrb[i]){
   
    (wstrb[i]) -> wdata[8*i+:8] inside {valid_byte};
  }};
 constraint c4{solve wstrb before wdata;}
  

endclass

module TB;
  Example E;

  initial begin
    E = new();
    repeat(10) begin
      assert(E.randomize());
      $display("wdata = 0x%x, wstrb = %b", E.wdata, E.wstrb);
    end  
  end
endmodule

If I don’t have “solve wstrb before wdata”, then wstrb remains zero (for all 10 randomizations I did).

Does that mean, the constraint solver needs to be specifically told of the order? If I didn’t specify the order, can it go either ways?

Appreciate any feedback. Thanks much!

2

See Constrain random variable result to enumerated type - #6 by dave_59

and

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