LRM :: "Assertion evaluation does not wait on or receive data back from any attached subroutine"

SystemVerilog
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1

I read the following quote from Section 16.11 of the LRM

Assertion evaluation does not wait on or receive data back from any attached subroutine

The first part of the quote is clear via the following sample code

   task  automatic  t1 ( int ip );
      #25 ;
      $display("At T:%2t task t1 completes with ip == %0d",$time,ip);
   endtask

   sequence s2;  //  Inherits  Clocking  Edge  from  property  'p2 '  !!
     (1, t1(d)) ##1  c ; 
   endsequence

   property p1 ;
     @(posedge clk) $rose(a) |=> s2 ;
   endproperty

   assert property( p1 ) ;

Evaluation of ‘c’ doesn’t wait for task ‘t1’ to complete.
‘c’ gets evaluated 2 clocks after $rose(a) is true ( irrespective of the delay within the task )

However I am not clear on the latter part ::

Assertion evaluation does not receive data back from any attached subroutine

If I were to write

 function int functn();
    return ( <expression_based_on_module_level_variables> );
 endfunction

  property p2 ;
     int  l1;
     @(posedge clk) $rose(a) |=> (1, l1 = functn() ) ##0 ( l1 inside {['hF0:'hFF]} );
   endproperty

   assert property( p2 ) ;

Here local variable ‘l1’ does receive data from subroutine ‘functn’ and only then using the returned value the expression ( l1 inside {['hF0:'hFF]} ) is evaluated.

So what does the latter part of the quote mean ?

2

Section 16.11 starts by saying

Tasks, task methods, void functions, void function methods, and system tasks can be called at the end of a successful nonempty match of a sequence.

Those are the subroutines that get scheduled to execute in the reactive region.

Your function functn is a non-void function. It gets evaluated as part of the expression it appears in.