Chris Spear, legendary author of “SystemVerilog for Verification,” UVM guru, and Principal Instructor from the Mentor Learning Center shares his 25 years of wisdom and desire to evolve those verification methodology skills that all design & verification engineers should have in their coding toolbox.
If you are building complex testbenches with SystemVerilog and UVM, this series is for you. The series dives into many aspects of these two areas, to give you deeper insight about how to apply the language and methodology on your projects. Whether you are new to SystemVerilog and UVM, or have been writing code for many years, take a fresh look at the fundamentals and learn some new ideas and approaches.
