Constrained Memory Block Allocation

SystemVerilog
1

I am trying to generate a constraint to allocate a block of memory in a given address range. This memory block should not overlap with a reserved memory region. Here are my constraints -

rand int unsigned mem_addr_start;
rand int unsigned mem_size;

constraint block_size_c {mem_size % 4 == 0;}; //Making the block 4B aligned
constraint addr_start_c {((mem_addr_start >= 8'hE0) || ((mem_addr_start + mem_size - 1) < 8'h20));
                           ((mem_addr_start + mem_size - 1) <= 8'hFF);};

Now, with the above constraints I expected the mem_addr_start to fall outside 8’h20 and 8’hFF, which is my reserved area. However, I do not see this happening. Would like to know the reason why.

When I modify block_size_c as below, I am getting the desired result. Why don’t I get the correct solution without using a range of values?

constraint block_size_c {mem_size inside {4, 8, 16};};
2

Your constraint addr_start_c does not handle overflow. Use 33'h20 and 33’hFF.

3

I am trying to understand your response, Dave. It is not clear to me the situation which would result in an overflow. Could you please elaborate with an example. Thanks.

4

Display the results you are getting with

function void post_randomize();
    $displayh(mem_addr_start,,mem_size,, mem_addr_start + mem_size - 1);
  endfunction
5

I got it. Prints did help to understand. Thanks, Dave!