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Creating Tests the PSS Way in SystemVerilog
Article - Jun 03, 2019 by Matthew Ballance
Portable Stimulus is one of the latest hot topics in the verification space. Siemens EDA, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test and Stimulus Standard, a standard language that can be used to capture Portable Stimulus semantics.
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Formal Bug Hunting with “River Fishing” Techniques
Article - Jun 03, 2019 by Mark Eslinger
Formal verification has been used successfully to verify today’s SoC designs. Traditional formal verification, which starts from time 0, is good for early design verification, but it is inefficient for hunting complex functional bugs. Based on our experience, complex bugs happen when there are multiple interactions of events happening under uncommon scenarios.
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Auto-Generating Implementation-Level Sequences for PSS
Article - Jun 03, 2019 by Amanjyot Kaur, Louie De Luna - Agnisys
The Portable Test and Stimulus Standard (PSS) v1.0a aims to help the user describe the high-level test intent and create code for any downstream verification platform.
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UVMF, Beyond the ALU Generator Tutorial Extending Actual Test Control of the DUT Inputs
Article - Jun 03, 2019 by George Stevens - DesignLinx Solutions
The basis of this article was derived from practical experience. The scenario was this: “Here is a DUT specification, we have no UVM environment for you to start with as a template, so go and find out how to generate one with Siem ens EDA ’s UVM Framework (UVMF) template generation methodology.”
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SystemVerilog Constrained Random Handbook
Resource (Reference Documentation) - May 28, 2019 by
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Random Directed Low-Power Coverage Methodology - A Smart Approach to Power Aware Verification Closure
Resource (Paper (.PDF)) - May 22, 2019 by Madhur Bhargava
With the advancement in the technology, low-power design and its verification is becoming more complex. Today’s chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels.
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Debugging Functional Coverage Models: Get the Most of Out of Your Cover Crosses
Resource (Paper (.PDF)) - May 13, 2019 by Mennatallah Amer
Applying hole analysis on each cover cross independently can lead to misleading results and is sometimes prohibitive due to the sheer number of crosses. Additionally, we introduce a metric, hole effect, that is proportional to the coverage gains that would result upon resolving the highlighted hole. We evaluate our approach on a real processor’s data processing unit to validate its applicability and usefulness for debugging complex functional coverage models.
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Debugging Functional Coverage Models: Get the Most Out of Your Cover Crosses
Paper - May 13, 2019 by Mennatallah Amer
Functional coverage models have grown in complexity to account for the increasing demands of designs today. Traditional and even advanced analysis techniques have yet to evolve to provide the verification engineer with actionable insights on how to debug their functional coverage model. In this paper, we generalize advanced hole analysis techniques to be able to get the most out of cover groups containing multiple cover crosses.
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UVM and C Tests - Perfect Together
Article - May 13, 2019 by Rich Edelman
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Block level testbench (.tgz)
Resource (Tarball) - Apr 19, 2019 by
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Verification Acceleration for ASIC and FPGA Designs
Resource (Slides (.PDF)) - Apr 09, 2019 by Jerry Grula - Siemens EDA
Modeling large integrated circuits for the workloads required for verification takes more computing than can be accomplished on CPU farms with 1000s of CPUs for many years.
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Don’t Do It Yourself: Questa VIP Accelerates UVM Testbench Development
Resource (Slides (.PDF)) - Apr 09, 2019 by Tom Fitzpatrick
This session will discuss writing constraints to characterize stimulus and configuration, creating prediction models, and defining coverage models with rapid testbench development utilizing the Questa Verification IP configurator to create high quality verification environments.
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No Testbench? No Problem! We Have a (Formal) App for That
Resource (Slides (.PDF)) - Apr 09, 2019 by Chris Rockwood - Siemens EDA
Formal verification uses mathematical and algorithmic methods to prove exhaustive results, requiring no testbench or stimulus.
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A Tale of Two Technologies - ASIC & FPGA SoC Functional Verification Trends
Resource (Slides (.PDF)) - Apr 09, 2019 by Harry Foster
This session discusses the Wilson Research Group Survey on ASIC and FPGA verification trends.
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Making Verification Fun Again
Resource (Slides (.PDF)) - Apr 09, 2019 by Bob Oden
The key characteristics of the UVMF: accelerate environment development, reusable, scalable, and emulatable.
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UVM Monitor
Resource (Tarball) - Apr 02, 2019 by
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Block level testbench
Resource (Tarball) - Apr 02, 2019 by
Example of a block level UVM testbench
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Five Steps to Quality CDC Verification
Paper - Mar 13, 2019 by Ping Yeung
With the number of clock domains increasing in today’s complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification.
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Formal Apps Take the Bias Out of Functional Verification
Paper - Mar 13, 2019 by Bill Au
An increasingly popular approach has been to employ a comprehensive, constrained-random, coverage driven testbench development flow, such as the Universal Verification Methodology (UVM). Indeed, when random stimulus generation is well executed it often finds bugs “that no one thought of.” However, this method’s success is limited to smaller DUTs as it is essentially impossible to do an exhaustive analysis of large, complex DUTs within a realistic project schedule.
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Five Steps to Quality CDC Verification
Resource (Paper (.PDF)) - Mar 13, 2019 by Ping Yeung
After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules.
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Formal Apps Take the Bias Out of Functional Verification
Resource (Paper (.PDF)) - Mar 13, 2019 by Bill Au
When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This why verification engineers have a blind spot for their own verification platforms. This blindspot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
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Technical Paper: UVM and C Tests - Perfect Together
Resource - Mar 03, 2019 by
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Effective Elements List and Transitive Natures of UPF Commands
Resource (Paper (.PDF)) - Feb 28, 2019 by
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The Big Brain Theory: Visualizing SoC Design and Verification Data
Resource (Paper (.PDF)) - Feb 28, 2019 by
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Using Strong Types in SystemVerilog Design and Verification Environments
Paper - Feb 28, 2019 by Dave Rich
One of the classic debates in computer science is whether a language should have a strongly-or weakly-typed data system. A strongly-typed language does not allow operations on data that are of incompatible types. Having strong types, as in VHDL, helps define intent and avoid errors, but is much more verbose.