Topics tagged interface

Topic	Replies	Views	Activity
Port mismatch while connect interface and dut SystemVerilog SystemVerilog , wire , logic , interface	3	3206	June 6, 2021
How to connect bi-directional signal UVM UVM , interface , systemverilog-uvm , bidirectional-port-inout-driver-interface	4	2065	May 24, 2021
Interface Port connection through a generate or array instance SystemVerilog SystemVerilog , interface , systemverilog-generate	0	1048	April 17, 2021
How to connect the inout port of class interface to inout port of module SystemVerilog SystemVerilog , interface , Inout-port	3	6575	April 5, 2021
Hierarchical access to a coverpoint from interface UVM SystemVerilog , UVM , Coverage , hierarchy , interface	1	856	January 16, 2021
Accessing interface signals inside sequence UVM UVM , interface , uvm-config_db	4	2480	December 28, 2020
Verification access to hierarchical signals without using hierarchical instance names SystemVerilog SystemVerilog , interface , verifcation	3	2137	October 19, 2020
Reuse task between multiple interfaces using package SystemVerilog SystemVerilog , interface , package-importing	2	1111	September 22, 2020
Skew in interface block SystemVerilog SystemVerilog , interface , clockingblock , skews	3	1237	August 17, 2020
Wire vs logic defination for signal of interface SystemVerilog SystemVerilog , interface , wire-logic	1	1099	July 20, 2020
Unexpected BUGS in "array of interface" and "array of modport" SystemVerilog SystemVerilog , System-Verilog , interface , array-of-interfaces , array-of-modport	1	1948	June 27, 2020
How to drive a reg/integer in a dut so as to avoid the error of Illegal combination of structural and procedural drivers UVM SystemVerilog , UVM , bind , interface , driver	1	4625	June 8, 2020
How to code interface of an agent in which the sequence item signals could be synchronous or asynchronous? UVM UVM , interface , asynchronous , clock-synchronous	1	1211	May 15, 2020
NULL pointer dereference UVM UVM , interface , Null-pointer-dereference	2	2041	April 30, 2020
Interface Connection UVM UVM , interface , monitor , activepassive-agent-configuration	3	1027	April 25, 2020
Sequence in UVM UVM UVM , sequence , interface , posedge-clk-begin , wait-statement	5	1365	April 22, 2020
Get a configuration class object in interface UVM UVM , assertion , interface	8	1596	March 9, 2020
Can you use 2 different instances of same interface to connect with each other in top module? SystemVerilog SystemVerilog , interface	3	1763	February 24, 2020
Connection between DUT and TB without Interface UVM UVM , DUT , interface	3	1660	February 22, 2020
Interface based Query SystemVerilog SystemVerilog , interface , systemverilog-interface , actual-interface	1	776	February 4, 2020
How to get uvm_config_db to accept a virtual interface that contains an interface in the port? UVM UVM , uvm_config_db , interface , Cookbook-EmulationExample	1	3779	January 12, 2020
Unable to pass interface signal by reference to a task UVM SystemVerilog , UVM , interface , pass-by-reference	2	2982	December 11, 2019
Interface related SystemVerilog SystemVerilog , interface	3	707	August 22, 2019
Interface syntax error UVM UVM , interface	2	6819	July 3, 2019
How to use Generate loop inside Interface to create clocking block SystemVerilog SystemVerilog , interface , Clocking-Block , Assertions-using-Generate-Block	4	5821	May 29, 2019
Properties encapsulation OVM OVM , interface , module , encapsulation , Properties	2	1634	April 11, 2019
Can we use a Class with encapsulation to do the work of an interface module? SystemVerilog SystemVerilog , interface	1	772	February 11, 2019
Connecting DUT and TB using interface without modports SystemVerilog SystemVerilog , modport , interface	18	4247	February 7, 2019
Multpile Dimensions for a interface/agents UVM UVM , interface , 2Darray	3	1441	January 18, 2019
Why interface can't be implicitly instantiated? SystemVerilog SystemVerilog , interface , Interface-Instantiation	2	1736	December 22, 2018