Clocking Block Skew @ Simulation Wave

SystemVerilog
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1

Hey!

I’ve encountered the following phenomena during the tweaking of my design to SV’s clocked interfaces. I’ve reproduced the result in Keisuke Shimizu’s Jelly Bean – UVM based – environment for easier access.
So, to my best knowledge if I declare a clocking block in the following way I should see a skew of the signals at the waveform simulation. But alas, no matter how I specify the parameters, the waveform stays the same. (The change at lines does always happen at the clocking block’s event occurrence.)

Relevant code sections:

interface jelly_bean_if( input bit clk );
	wire [2:0] flavor; // All variables are wires.
        ...

	clocking master_cb @ ( posedge clk );
		default input #1step output #3ns;
		inout flavor, color, sugar_free, sour;
	endclocking: master_cb

	modport master_sync_mp	( clocking master_cb );
endinterface: jelly_bean_if

class jelly_bean_driver extends uvm_driver#( jelly_bean_transaction );
   `uvm_component_utils( jelly_bean_driver )

	virtual jelly_bean_if jb_vi;
	jelly_bean_transaction jb_tx;
	...
	task run_phase( uvm_phase phase );
		forever begin
		@jb_vi.master_cb;
			...
			jb_vi.master_cb.flavor <= jb_tx.flavor;
			...
		end	//	forever begin
	endtask: run_phase
	
endclass: jelly_bean_driver

This result in QuestaSim 10.2c in the following waveform:

Link if the picture is not working.

I might not be fully aware of the clocking block’s function, but shouldn’t it delay the output on the interface via the defined amount of time?

I’ve found a workaround for this matter also, but I think if the output skew is defined it would be a much better way to handle this matter.

@jb_vi.master_cb;
	...
	begin
		#2ns;
		jb_vi.master_cb.flavor     <= 'z;
		...
	end	
	...
end

All help is appreciated.

2

hi .
Might be you are seeing the signal which come under the clocking block master_cb hierarchically.
If you take look on the the signal which are just come under the interface (signals declare outside the clocking block), i think there you can see the delay . What i think that ,when you declare clocking block ,it make its own set of signals which are declared into it , For output : Signals with in the clocking block take the output values at clock posedge but drive on the real interface (signals declare outside the clocking block) after the delay specify.

3

I am also seeing the same behavior.
Is there any update OR feedback on this query ?

Regards
Manasa.U