Interface based Query

SystemVerilog
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1

I have the following queries wrt Interface construct in SV:

  1. Why is it recommended to drive the interface signals via a Non-Blocking Assignment?
  2. The DUT evaluates its logic and drives the outputs to the Testbench through clocking blocks. I read that the outputs are sampled in the postponed region. Why does this happen?
2

In reply to atanubiswas:

https://verificationacademy.com/forums/systemverilog/driving-wire-task-interface.

https://verificationacademy.com/forums/systemverilog/question-regarding-sv-region/scheduling-class-vs-program

Also see my diagram for timing zones.
See Sampling point of Assertions | Verification Academy

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