module A (
req
,clk
);
input req;
input clk;
always @ (posedge clk )
begin
state_reg <= START;
end
reg [1:0] state_reg=INVALID;
-
<REST OF THE CODE in module A>
endmodule
My interface :
interface A_if(inout state_reg)
task force_reset();
force state_reg = 2'b11;
endtask
endinterface
I get this error:
Illegal combination of structural and procedural drivers.
Variable “state_reg” is driven by an invalid combination of structural and
procedural drivers. Variables driven by a structural driver cannot have any other drivers.
Note I cannot change the dut code i.e (module A) and this is just a dummy code, written to convey the issue.