How to use Generate loop inside Interface to create clocking block

SystemVerilog
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1

Hello ,

Can anyone have idea how we can use generate statement in interface file to create a clocking block ?

Currently trying with :

 interface abc_if #(int NO_Input=3);

  logic [NO_Input-1 :0 ] xyz_o;   
  logic [NO_Input-1 :0 ] clk_i;

   genvar i;
   generate
   for(i=0;i<NO_Input;i++)begin 
   clocking abc_cb @(posedge clk_i);
       output xyz_o;
   endclocking 
   end
   endgenerate
   endinterface

Regards,
Nidhi

2

In reply to nidhigandhi:

Did you mean to write:

interface abc_if #(int NO_Input=3);
 
  logic [NO_Input-1 :0 ] xyz_o;   
  logic [NO_Input-1 :0 ] clk_i;
 
   for(genvar i=0;i<NO_Input;i++)begin : block
      clocking abc_cb @(posedge clk_i[i]);
         output xyz_drive = xyz_o[i];
   endclocking 
   end : block
// then you can drive 
    block[0].abc_cb.xyz_drive <= '1; // drives xyz_o[0]
endinterface

Note that you will need to index block[n] where n is a literal constant or parameter.

3

anybody pls give me idea,
how to assign one interface definition with two same address[31:0] and address[7:0] signal declaration in systemverilog

4

In reply to dave_59:

In reply to nidhigandhi:
Did you mean to write:

interface abc_if #(int NO_Input=3);
logic [NO_Input-1 :0 ] xyz_o;   
logic [NO_Input-1 :0 ] clk_i;
for(genvar i=0;i<NO_Input;i++)begin : block
clocking abc_cb @(posedge clk_i[i]);
output xyz_drive = xyz_o[i];
endclocking 
end : block
// then you can drive 
block[0].abc_cb.xyz_drive <= '1; // drives xyz_o[0]
endinterface

Note that you will need to index block[n] where n is a literal constant or parameter.

This piece of code is not working for me.
I see error “Clocking blocks are not allowed in this type of design unit [SystemVerilog]”
Without for loop it is going good but I need clk_i[i]. What can be the issue ? Thanks !

5

In reply to Andee:

The issue is your simulator. Try a different one.