Topics tagged UVM

Topic	Replies	Views	Activity
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	20	18499	February 22, 2024
Scoreboard with multiple analysis connections to a single monitor class UVM SystemVerilog , UVM	0	107	February 21, 2024
Extract $bits and component name from interface SystemVerilog UVM	1	71	February 21, 2024
Confusing implementation of scoreboard UVM UVM , clone , virtual , UVM-scoreboard	4	893	February 20, 2024
Raise_objection/ drop_obejction UVM UVM	2	133	February 13, 2024
What is the best option for model a memory? UVM UVM , uvm-memory-agent	13	892	February 13, 2024
UVMF multidimensional interface ports and transaction fields UVM UVM	1	116	February 12, 2024
Sequencer and pull port being cleared to null between Build and Connect phase UVM SystemVerilog , UVM	1	132	February 7, 2024
Sending data from monitor to sequence UVM UVM	35	8390	February 6, 2024
Uvm_config_db in an interface UVM UVM , uvm_config_db	3	5537	February 5, 2024
$monitor vs uvm_info UVM UVM	1	165	January 31, 2024
Connecting inout real to real data type SystemVerilog UVM , Coverage , assertion , System-Verilog , SVA	1	137	January 30, 2024
Named events within property SystemVerilog UVM , SVA , assert-property , Named-events	3	89	January 29, 2024
Introduction to UVM UVM UVM	1	179	January 28, 2024
Getting fatal error while doing uvm_config_db get method in scoreboard UVM UVM	3	144	January 26, 2024
Difference between arbitration queue and request fifo UVM UVM	1	170	January 26, 2024
Bind a module, with parameters not from the target location SystemVerilog UVM	4	128	January 26, 2024
Not able to open file in read mode UVM UVM	4	4335	January 25, 2024
Testing UVM Components with UVM-UTest UVM UVM , SVUnit	0	134	January 25, 2024
UVM Ral model Backdoor is not working UVM UVM	2	203	January 23, 2024
Passing the environment configuration UVM UVM	0	122	January 19, 2024
Using of UVM Config dB UVM UVM	1	141	January 19, 2024
Importing package again if this is defined in another package, UVM UVM	7	1078	January 17, 2024
How to use set_report_severity_id_override for a UVM_WARNING within base test? UVM UVM	5	4038	January 16, 2024
Which region does Testbench use to drive the signal to DUT? UVM SystemVerilog , UVM , timing-control , timing-regions	3	1532	December 14, 2020
Not registered with the factory UVM UVM	10	11641	January 15, 2024
Randcase usage to get all possible values of logic (four state) data type SystemVerilog SystemVerilog , UVM , System-Verilog	2	121	January 14, 2024
How to get(access) the data members(properties) of sequencer from driver? UVM UVM	6	127	January 10, 2024
While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value UVM UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model	2	281	January 10, 2024
How to get handle to env from the sequence in uvm? UVM UVM	11	4594	January 10, 2024