Named events within property

SystemVerilog
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1

I have a very smilar code as given below in an UVM testbench. A named event gets triggered from a uvm_component and there is an asserted property which should start evaluation. Unfortunately SVA doesn’t get triggered even though event seems triggered within assertion thread. Is it due to event regions somehow its sampled value never gets triggered? But below code successfully runs as expected when I tested in edaplayground.

module tb;
  
  bit clk=0;
  
  initial begin
    clk = 0;
    forever begin
    	#10; clk=!clk;
    end
  end
  
  event e;

  property event_prop();
    @(e) ##0 1 |-> @(posedge clk) ##1 1;
  endproperty

  assert property(event_prop) $display("Passed %0t", $realtime);

    class A;
      task trig();
        #5;
        ->e;
      endtask
    endclass
  
  initial begin
    static A a = new();
    a.trig();

    #5;
    ->e;

    #20;
    
    ->e;
    #50;
    $display("end");
  end

endmodule

2

Ben] UVM is not static. In this paper (link to be fixed) I show a way to use assertions in a UVM env.
https://verificationacademy.com/verification-horizons/fFebruary-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
You basically need to copy your variables/events into an interface.
Assertions in the interface or modules can then see those variables/events.
This has nothing to do with event regions.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

3

Hi Ben,
Link you’ve attached is broken. Other than that, I’m using the trigger mechanism via virtual interface handle obviously.

4

Ok looks like I’ve found the problem. The more I added the implementation closer to the actual one, tools started to complain about event assignments. Luckily other options available in edaplayground revealed the bug,

interface event_if;
  event if_e;
endinterface

class A;
      
  virtual interface event_if intf;
        
  task trig();
    #5;
    ->intf.if_e;
  endtask
    
endclass

module tb;
  
  bit clk=0;
  
  initial begin
    clk = 0;
    forever begin
    	#10; clk=!clk;
    end
  end
 
  event_if event_if();
    
  event e[5];
  assign e[0] = event_if.if_e;  // bug here
  
  property event_prop();
    @(e[0]) ##0 1 |-> @(posedge clk) ##1 1;
  endproperty

  assert property(event_prop) $display("Passed %0t", $realtime);
        
  initial begin
    static A a = new();
    a.intf = event_if;
    a.trig();
    
    #20;
    ->e[0];

	#50;
    $display("end");
    $finish;
  end
  
    endmodule