UVM Ral model Backdoor is not working

UVM
1

I have created an Arithmetic Logic Unit (ALU) that supports addition, subtraction, multiplication, division, and modulus operations. The ALU comprises registers such as regA, regB, regC, operation_type, and sfr. The registers regA, regB, and operation_type are designated as write-only, while regC and sfr are marked as read-only. Specifically, regA represents operand 1, regB represents operand 2, and operation_type determines the operation to be executed. The result of the operation is stored in regC, and the sfr register contains flags indicating carry, overflow, sign, and zero.

Despite my attempts to write values into regA through a backdoor, I have encountered difficulties. The issue persists even when using VNC, as no error messages are displayed. I have experimented with different approaches to address the problem, but none have been successful. It’s worth noting that this ALU design and the associated verification environment are custom-made for the purpose of studying RAL (Register Abstraction Layer) models.

If anyone can provide assistance or guidance on resolving this issue, it would be greatly appreciated.

[code link]
(alu - EDA Playground)

2

It seems something is wrong with your register model. When replacing the regA write/Backdoor with poke which is assigned to be a backdoor write I’m facing an error. This should not happen.
Now I had a closer look to your problem. You are relying on the default value of the bit declaration for regA. When you are doing a poke with this data it receives a value different form 8’h00.
When you are assigning regA to 0 like this
regA = 8’h00 prior to the poke anything is fine.

3

Please set the top path for backdoor access in ie_env.sv In the build phase, please add the below line.
begin
string hdl_root=“ei_top.”;
void’($value$plusargs(“ROOT_HDL_PATH=%s”,hdl_root));
reg_block_h.set_hdl_path_root(hdl_root);
end
I hope this will help you.

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