Extract $bits and component name from interface

SystemVerilog
1

Dear all,

I would like to extract size and the element name from hierarchically build interface which include packed struct and this struct include another struct. How this could be done if it could be done at all? Here is an roughly what I would like to do:

package test_pkg
  typedef struct packed {
     logic  aa1 ;
     logic  aa2 ;
     logic  aa3 ;
} aa_td;
typedef struct packed {
     aa_td  aa ;
     logic  bb1 ;
     logic  bb2 ;
 } bb_td;
endpackage : test_pkg

interface first_interface;
  bb_td    bb;**
  logic      cc1;**
  logic      cc2;**
endinterface**

virtual first_interface    first_if;

now I would need to do something like :

num_of_element = $bits(first_if)      // I am expecting 3+2+2 =7 bits
for (int i=0; i < num_of_element; i++) begin 
        $display("Name first_if[%d] = %s", i first_if[i].name()); // first_if[0] = cc2 .... first_if[6] = aa1
    end

Any suggestion would be welcome?
Thanks and best regards.

2

This is what is known as introspection which is not directly part of the SystemVerilog language. There is an programming interface to get access to this data (see Introspection Into SystemVerilog Without Turning It Inside Out), but probably not the most efficient mechanism depending on what you are ultimately trying to accomplish.