Introduction to UVM

Hi All,

About introduction to UVM…

UVM was designed to be more modular and reusable, with a clear "separation between testbench components and the design-under-test (DUT) "


One of the main feature of UVM is “Seperation of test from testbench”

I would like to understand what is the meaning of seperation or how do we understand “test is seperated from TB” ?

Ideally both SV top TB file and UVM top TB file looks similar. The only difference in UVM top TB file is calling “run_test”, rest everything reamins same from SV TB.

Could you please clarify the above mentioned point?

Thank You,

An analogy is the testbench is like an orchestra and the test is the sheet music that represents the symphony or compositions. If you were planning a concert with 10 compositions, you need to construct an orchestra with the right instruments, even though each instrument might not be used for every composition.

The testbench is the architecture of components that executes the test. You build the testbench before running the test but the test needs to direct what goes into the testbench.

In the UVM, the run_test task chooses which test to execute, and the first thing the test does is build the class based testbench architecture of uvm_components. It then enters the run_phase until the test decides when to end.