I want to code an agent to emulate a RAM. The memory is outside of the DUT, and I want to test its memory handler. My question is:
What is the best option in UVM to do that? My first thought was to create a component inside the agent for doing the storage, that communicates with the driver and monitor to read/write the data. But I couldn’t figure out how to connect them, what type of component should I use, and what type of variable should I use
I couldn’t find much information about this. I would like to have some ideas to start coding.
In reply to kevinvig7:
You want to use a slave sequence or a separate slave agent. See Sequences/Slave | Verification Academy
In reply to dave_59:
Thanks, David! That helped me a lot!
Is there anyway to access the memory inside slave sequence from scoreboard for backdoor comparison?
And data you want to share should be put into a class object and its handle shared with the uvm_config_db.
I have one more question.
In my case, I have memory inside the sequencer. How can scoreboard access the sequencer memory ?
My approach is put the sequencer memory inside an object.
Rough code example:
class mem_class extends uvm_object;
class sequencer_extends uvm_sequencer;
function void build_phase(uvm_phase phase);
In scoreboard, just declare that memory class handle.(No object creation)
class scoreboard extend uvm_scoreboard;
In environment, connect the scoreboard memory class handle(mem_obj_scb) to sequencer memory object(mem_obj_sqr).
Is this approach correct?
Is there any 2nd approach to do this?
Your mem_class needs a constructor and it should be registered with the factory.
Nn the build_phase of the ssequencer I’d call the create method of the factory.
But the key question is why do you need the memory in the sequencer. In my eyes this is wasting of resources.
I’m working on reactive agent with memory. Below is my uvm architecture.
I implemented the sampling logic inside monitor. Driver is capable of only driving.
Whenever there is a REQ, monitor captures it and send it to sequencer using TLM port connection into TLM fifo.
Sequencer reads the TLM fifo content and checks if it is READ or WRITE transaction.
If WRITE, it writes into memory.
If READ, sequence will read the memory using p_sequencer handle and send the RESP(read data)
I do not understand what the content of the STORAGE is. Does it mirror a memory in the DUT?
Then I recommend to use the UVM RAL with uvm_mem. This provides you with all the emachnisms you need.
Sorry I misunderstood your previous question and I replied as “Yes”.
I’m developing memory model VIP. I don’t have a DUT.
Hi Christoph/ Dave,
STORAGE is a class containing systemveriog array, write and read functions.
i may be wrong,
since this memory is shared and visible to all components,
you can assign the handles of memory object in agent or can use config db set (since the handles where we have used get will point to the same memory) in higher hierarchy.
may be wrong ,uvm_objects are transients won’t it affect in any way?