Topics tagged UVM

Topic	Replies	Views	Activity
Uvm reset during normal transaction UVM UVM	1	114	March 21, 2024
Deep copy in System Verilog SystemVerilog SystemVerilog , UVM , shallow-copy , deep-copy , deep-copy-and-shallow-copy , copy-method	1	93	March 20, 2024
Monitor to test connection UVM UVM	3	75	March 19, 2024
2 process writing on an analysis port from monitor UVM UVM , analysis-port , UVM-monitor , uvm_monitor-uvm_scoreboard-write	11	737	March 18, 2024
Question regarding uvmf_in_order_scoreboard_array and uvmf_out_of_order_scoreboard UVM UVM	1	422	May 23, 2022
Uvm_config_db set method clarification UVM UVM , uvm_config_db	0	88	March 13, 2024
Uvm_sequencer setup UVM UVM , sequencer	1	82	March 12, 2024
UVM on uvm_config_db clarification UVM UVM , uvm_config_db	1	85	March 11, 2024
UVM - db_config question on parameterization UVM UVM , uvm_config_db	0	73	March 11, 2024
UVM Cookbook Scoreboard Doubt UVM UVM , Cookbook-Scoreboards	2	96	March 10, 2024
UVM RAL: Can we always use backdoor access instead of frontdoor access? UVM UVM , uvm-ral , UVM-RAL-back-door-peek	2	586	March 9, 2024
The use of virtual interface in uvm_monitor UVM UVM , UVM-monitor	1	92	March 8, 2024
The object at dereference depth 3 is being used before it was constructed/allocated.Please make sure that the object is allocated before using it UVM SystemVerilog , UVM	1	254	March 8, 2024
Driver Response to Sequence UVM UVM , sequencer , driver	7	138	March 7, 2024
Associative array of class based data type SystemVerilog OVM , SystemVerilog , UVM	1	93	March 7, 2024
Specifying default values to constructor of user classes extended uvm_object and uvm_component UVM UVM , default-values-to-constructor-of-user-classes-extended-uvm_object-and-uvm_component	3	693	March 6, 2024
Necessity of writing 'include "uvm_macros.svh" UVM UVM , uvm_macrossvh	12	11331	March 1, 2024
RAL Backdoor access, set hdl paths UVM UVM , RAL	1	106	February 29, 2024
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	24	19310	February 29, 2024
There are 2 agents. can Monitor from agent A communicate with Sequencer of Agent B. If yes how? UVM UVM , testbench	3	170	February 28, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	99	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	152	February 25, 2024
Use of an Associative array or Queue in System Verilog Assertion Property SystemVerilog SystemVerilog , UVM , assertion , System-Verilog , queue , property , accessing-the-associative-array-elements	6	163	February 23, 2024
How to do multiple instance of same agent? UVM UVM , how-to-do-multiple-instance-of-same-agent	16	2348	February 22, 2024
Pass variable from test to sequence UVM UVM	9	6278	February 22, 2024
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	20	18456	February 22, 2024
Scoreboard with multiple analysis connections to a single monitor class UVM SystemVerilog , UVM	0	100	February 21, 2024
Extract $bits and component name from interface SystemVerilog UVM	1	64	February 21, 2024
Confusing implementation of scoreboard UVM UVM , clone , virtual , UVM-scoreboard	4	878	February 20, 2024
Raise_objection/ drop_obejction UVM UVM	2	125	February 13, 2024