Uvm_config_db set method clarification

UVM
,
1

Hi everybody,

Just got a question on trying to figure out the interpretation of the set method I have in the code below I will be providing:

`include "uvm_macros.svh"
import uvm_pkg::*;

`include "ex_interface.sv"
`include "ex_test.sv"
`include "ex_design.sv"

module tb_top; 
    bit clk, reset; 

    always #5 clk = ~clk; 

    initial begin
        reset = 1; 
        #2
        reset = 0; 

    end

    // virtual interface
    adder_if vir_interface(clk, reset);
    // need the DUT
    adder DUT(.clk(vir_interface.clk), .reset(vir_interface.reset), 
              .in1(vir_interface.input_1), .in2(vir_interface.input_2), .out(vir_interface.result));


    initial begin
        uvm_config_db#(virtual adder_if)::set(uvm_root::get(),"*","the_interface",vir_interface);
        run_test("the_test");
    end

endmodule

The part I need help in interpreting is the line of

uvm_config_db#(virtual adder_if)::set(uvm_root::get(),"*","the_interface",vir_interface);

Particularly, what does uvm_root::get() return? Is it the path of the root of hierarchy of the uvm components that I have laid out?

Sincerely,

Sangwoo

2

the “uvm_root” static get method returns a reference to the top-level “uvm_root” object which is base class in uvm bench